ML20206S268

Forwards Description of SPDS Isolation Methodology Based on Discussion at 870407 Meeting.Method Will Provide Isolation When Exposed to Max Credible Fault.One Oversize Drawing Encl

ML20206S268
Person / Time
Site:	Rancho Seco
Issue date:	04/17/1987
From:	Julie Ward SACRAMENTO MUNICIPAL UTILITY DISTRICT
To:	Miraglia F Office of Nuclear Reactor Regulation
References
JEW-87-619, TAC-56525, NUDOCS 8704220365
Download: ML20206S268 (9)

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SACRAMENTO MUNICIPAL UTILITY DISTRICT C P. O. Box 15830. Sacramento CA 95852-1830,(916) 452-3211 AN ELECTRIC SYSTEM SERVING THE HEART OF CALIFORNIA TAPR 171987 JEW 87-619 Director of Nuclear Reactor Regulation Attention: Frank J. Miraglia, Jr.

Division of PWR Licensing-B U S Nuclear Regulatory Commission Washington D C 20555 Docket 50-312 Rancho Seco Nuclear Generating Station Unit #1 SPDS ISOLATION METHODOLOGY

Reference:

J. E. Ward to F. J. Miraglia Jr., CRDR/SPDS Response to NRC Questions, 3/30/87

Dear Mr. Miraglia:

A ceeting at Rancho Seco was held with members of the NRC staff on April 7,1987 to discuss the District's isolation design and philosophy for SPu3. During this meeting, the participants discussed several alternative designs. Attachment 1 describes a mutually acceptable isolation approach that the District will implement. The method will provide isolation when exposed to the maximum credible fault. Attachment 2 displays the SPDS block diagram showing power supplies, signals and Class 1E and non-Class 1E interfaces.

This diagram provides a basis for the isolation discussion in Attachment 1 and resolves several items in Attachment 2 of the Reference.

If you have any questions, please contact John Atwell of my staff. -

Sincerely,

. Ward Deputy General Manager, Nuclear Attachments cc: George Kalman, NRC - Bethesda A. D'Angelo, NRC - Rancho Seco 870422036S 870417 PDR ADOCK 05000312 O\

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DISTRICT HEADQUARTERS O 6201 S Street, Sacramento CA 95817-1899 i

l ATTACHMENT 1 SPDS ISOLATION METHODOLOGY 4/8/87 I

The following discussion provides a description of the isolation boundaries, modifications to the isolators and the maximum faults applicable to each of the isolators. All references to the block diagram refer to the drawing in Attachment 2 to this letter.

During the April 7, 1987 meeting with the NRC staff, the District and NRC i representatives discussed several alternatives for providing isolation in the l SPDS. As a result of this discussion, the District evaluated the alternatives available and will augment the existing design by the use of fuses and physical protection to assure proper isolation.

1.0 Multiplexer Isolation 1.1 General Isolation is provided between each nultiplexer and the Channel A &

B data buses and in the case of Universal Field Multiplexer (UFM)

1. 1, isolation is also provided between the non-Class 1E sensor inputs and the Class 1E multiplexer. The remaining non-Class 1E sensor inputs to the multiplexers are located in non-Class 1E cabinets and thus, do not require isolation.

1.2 Isolation Boundary The data bus isolation boundary for non-Class 1E multiplexers l number 4, 6, 8,10 (UFMs) is provided by leolator number 8. These isolators are located in the Class 1E multiplexer (UFM's 3, 5, 7, l 9) cabinets as shown on the block diagram. Multiplexer number 2 is isolated from the data bus by the number 8 isolator located in the UFM #1 cabinet. Thus, each of the remote non-Class 1E multiplexers are isolated, including multiplexers and sensor inputs from the j data bus by isolator number 8.

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Multiplexer number 1 is a class 1E multiplexer which receives non-Class 1E sensor inputs. These sensor inputs are isolated from the multiplexer by isolators 4 and/or 5. This isolation provides the boundary between the Class 1E multiplexer #1 and the non-Class 1E inputs. All Class 1E powered multiplexers (UFM's 1, 3, 5, 7, 9) are isolated from the data bus by the isolators (#8) located in each individual cabinet.

The Class lE sensor inputs are power train separated by having all train 'A' powered sensors enter UFM's 3 & 7 and all train 'B' powered sensors enter UFM's 5 & 9. Thus physical separation is l provided between power trains & inputs and no isolation devices are necesaary.

1.3 Isolators The method of data bus isolation from the multiplexers is via the number 8 isolator. These devices are currently bus isolators with adjustable attenuation. As a result of discussions with the staff, these isolators will be augmented by inserting fuses in the

1.3 Isolators attenuation circuit. The addition of fuses in the circuit will assure that the maximum fault will not propagate beyond the isolator to the data bus and potentially cause a loss of the bus.

All number 8 isolators shown in the block diagram will be augmented by the insertion of a fuse. The fuses will be encapsulated (e.g.

potted) on the isolator boards to preclude the possibility of field maintenance (i.e. fuse replacement) on the boards. The encapsulation method used will not interfere with the proper operation of the circuit. Physically, encapsulation of the fuses will, at a minimum, include the fuses and its connectors to ensure the fuse can not be removed or short circuited. The augmentation of the board by encapsulation will be proceduralized to ensure consistency in its application. All fuses used in this application will be of a high quality and reliability by meeting Hilitary Standard 202 requirements.

Having prevented field replacement of the fuse, physical protection of the bus isolators (#8) is also provided. Attachment 3 contains a conceptual sketch of the physical protection which will be provided for each bus isolator found in the multiplexer cabinet. This protection adds further assurance that there will be no accidental means of compromising the isolator as well as providing additional separation between the SPDS channels.

The non-Class 1E sensor inputs to UFM #1 are isolated by isolators 4

& 5. Isolator number 4 is an optical isolator and is used for all digital inputs. For analog inputs to UFM #1 isolator number 5 provides transformer coupled isolation.

1.4 Testing The District has reviewed the locations of isolators 4, 5 & 8 for the maximum fault potential. All multiplexer cabinets are exposed to sources of 120 VAC power while UFMs 4, 7, 8, 9 & 10 have the potential for 140 VDC from one or more of the sensor inputs. Based on this, the number 8 isolators will be tested fcr the maximum fault application of 120 VAC and 140 VDC power sources. The District is in the process of testing the isolators and upon completion of the testing, will provide the staff the final test report.

The number 4 & 5 isolators were tested by the vendor. The District is currently evaluating the results of this testing. If the District {

determines the testing to be applicable, it will transmit the results to the staff. However, if the testing does not encompass the maximum faults (120 VAC & 140 VDC), the District will authorize additional testing and forward the results to the NRC.

The District will send the test results for isolators 4, 5 & 8 to the NRC staf f in May 1987.

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2.0 -Interim Data Acquisition and Display System (IDADS) Computer Isolation-

'2.1 General The non-Class 1E IDADS computer has two interface points with each of

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the Class 1E Central Control Units (CCU). One of these interfaces-indicates the status of the CCU while the other allows the two way.

interface between the CCU & IDADS. Thus these points need ~ isolation to ensure that a fault occurring in the non-Class 1E IDADS computer does not propagate to the Class 1E CCU.

i 2.2 Isolation Boundary e

The two number 9 isolators found in the Class 1E CCU cabinets provides isolation between CCU's 1 & 2 and the IDADS computer.

Originally one of these interface points was isolator number 11.

Based on the discussions with the staff, the number 11 isolators are to be replaced by number 9 isolators. This change has been reflected in the block diagram.

2.3 Isolators [

Isolator number 9 provides isolation by using a transformer with a fuse installed in one side of the transformer input. A second fuse will be inserted on the other side of the transformer input. As described in Section 1.3, the fuses in this isolation circuit will be encapsulated in the same manner to preclude field modification of the circuit (i.e. fuse replacement). Physical protection from accidental tampering with the board is assured by the location of the board on which the isolator is located. Since the board containing the isolator is in very close proximity with other circuit boards in the card case, the entire circuit board on which the isolator is located requires removal before any work is possible on the board. This protection method will cause, during maintenance activities, an ,

opening of the circuit preventing the isolation function from being compromised.

2.4 Testing ,

Review of the IDADS computer indicates the maximum fault to which the ,

isolator could be exposed is 120 VAC. The District's vendor tested  ;

isolator number 9 to a 120 VAC fault and the isolator passed the test by not allowing the voltage to propagate to the Class 1E side of the isolator. The District is reviewing the test report and upon completing this review and additional testing with the added fuse and encapsulation, the tests results will be provided to the NRC staff.

The District will submit the final report to the NRC staff in May l 1987.

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3.0 CCU Select Unit (CSU) Isolation 3.1 General The CSU interfaces with both CCU's thus isolation between the two channels of SPDS is necessary. Isolator number 10 shown on the block diagram provides this isolation.

3.2 Isolation Boundary With the CSU being a common contact between the two channels of SPDS, isolation must be provided to prevent a failure in the CSU from propagating to either of the CCU's. The number 10 isolators in the CSU (see block diagram) establishes this isolation boundary. If a fault were to occur in a CCU its propagation would be prevented by the number 10 isolator found in each CCU as well as those located in the CSU.

3.3 Isolators The optical isolation device denoted as isolator 10 in the block diagram furnishes isolation between the CCU's and the CSU. Thus a fault occurring in any CCU or in the CSU, is isolated from the other channel by several isolation devices. This optical device provides positive assurance that no fault will propagate between SPDS channels within the H4CDAL cabinet.

3.4 Testing Isolator nunber 10 is located within the H4CDAL cabinet which the District evaluated for the maximum fault. As shown on the block diagram, 120 VAC is available in the cabinet and is therefore the maximum voltage to which the isolation device enn be exposed. The isolation device has been tested with the application of a 120 VAC fault and the test results are under evaluation.

Upon final review and approval, the District will forward the test results to the NRC staff in May 1987. I 4.0 Conclusion The District evaluated alternative methods of isolation and determined that the most effective means of providing proper isolation of the SPDS would be through the installation of fuses in several of the isolators augmented by physical protection. This method will provide assurance that proper isolation will occur. As noted, testing is in various stages of completion. However, the District anticipates no problems in showing by test, that proper isolation occurs. Based on this discussion, the District considers the SPDS isolation methodology to be acceptable.

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s ATTACHMENT 2 SPDS BLOCK DIAGRAM

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SIDE VIEW 1 COVER PLATE.

2 BUS DIVIDER PLATE 3 SPACER 4 BUS ISOLATOR BOARD ,

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