ML20212M447

Rev 1 to Procedure EIP-37, Integrated Functional Test Procedure for Analog & Digital Isolation Sys,Including Design Basis Sys Fault Testing

ML20212M447
Person / Time
Site:	South Texas
Issue date:	10/24/1986
From:	ENERGY, INC.
To:
Shared Package
ML20212M416	List: ML20212M414 ML20212M420 ML20212M425 ML20212M447 ML20212M477 ML20212M492 ML20212M591 ML20266D945 ML20266D949 ML20266D954 ST-HL-AE-1917, Marked-up Schematic Diagram - Relay Logic. Sheet 2 of 5
References
EIP-37, ST-HL-AE-1917, NUDOCS 8703120026
Download: ML20212M447 (18)

Text

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• ** ATTACHMENT J ST.HL AE 191T

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PROCEDURE

'I INTEGRATED FUNCTIONAL TEST PROCEDURE FOR THE ANALOG AND DIGITA

!$0LAT!0N SYSTEM, INCLUDING DESIGN BASIS SYSTDt FAULT TESTING f

DATE PREPARED 3Y *M #b 6 hlW [

REystwEn my A SN RELEASE DATE '

8/12/85 l GUALITY ASSURANCE VE AJA > A /J-13 PRgpARgO FOR l PROJECT MANAGER I # 6 --

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f REvlsioNs Et Allrevisionsareflaggedwiththesymbolbintherightmargin

, where N is the number of th4. reifafon

, Rev. 0 - Issued for Use - 8/12/85 Rev. 1 - Complace revision of procedure - 9/17/85 M e N W'rfW O E9888A' E89j,p FORINFORMAIl N ONLY asus o m OCT 241986 PROCEDURE NO.

EIP-37 2(1.)  !

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~ ~ TABLE OF CONTENTS PAGE 1.0. SC0PE............................................................... 5 2.0 RESPON5 ! B I L ITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 REFERENCE 00CUENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 .

4 4.0 TEST EQUIPMENT MQUIRED............................................. 6 5.0 TEST PR0CEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 7 4

5.1 Protest........................................................ 7  :

5.2 Test Setup ( Functional and Input Faul t Test) . . . . . . . . . . . . . . . . . . . 7 .

5.3 Func ti onal and Input Faul t Test Procedure . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Test Setup ( Func tional and Output Faul t Test) . . . . . . . . . . . . . . . . . 10  !

5.5 Func ti onal and output Fa ul t Tes t Procedure . . . . . . . . . . . . . . . . . . . . 12 l

4.0 POWER SOURCE INPUT FAULT TEST 1NG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 j 6.1 5e tu p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 j 6.2 Functional and Power Source Fault Test Procedure..............14 i

7.0 ACCEPTANCE CRITERIA................................................ 14 8.0 POSTTEST INSPECT 10N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.0 FINAL REVIEW....................................................... 15 ATTAC K NTS

. ATTACHMENT 1 ATTAC M NT 2 '

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navismN NO. PROCEDURE N O. E!P-37 1

PAGE1 0F 16

6. c.t.-i4e. . . . ..

TAiLE OF CONTENTS (continued)

' DATA SHEETS

• 1 IDENTIFICATION OF !$0LATOR M000LES 2 SYSTEM INPUT FAULT TEST 4

3 SYSTEM OUTPUT FAULT TEST 4 POWER SOURCE FAULT TEST 5 POSTTEST INSPECTION / FUNCTIONAL TEST l

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navassON NO. PROCEDURE NO. E!p.n 1

PAGE 2 0F 16 a - .. -

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LIST OF TABLES E .T.lij [,

• PAGE 1 APPLIED FAULT.' MONITORING, AND ACCEPTANCE CRITERIA SUMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 i

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LIST OF FIGURES M TITLE -

PAGE

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&sta Input Faul t Test 5etup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a i 2  % stem Output Faul t Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Faul t Test on Power Supply Li ne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 27.3 navislON NO. ~ ' PROCEDURE NO.. EIP-37 1 PAGE 4 0F 16

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1.g 3,gyg This procedure describes the method and steps to be followed uh'en per-feming an integrated system fWu:tional test and plant-specific design basis fault test en the analog and digital isolation system.

The test methodology provides adequate incorporation of previously type-tested analog and digital isolation modules with deliverable modules into a functioning system. The design basis credible fault possible is applied to l the type-tested modules. The required design electrical inputs are concur- t rently applied to the representative deliverable modules.

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, App 1tcation of credible fault to power input lines that are greater than

{ design conditions will require exclusion of the deliverable modules from l

l the common mother bus. This is done simply to protect damage to the deliv-I erable modules.

1 i

2.0 RESP 0N518!LITIES

! 2.1 Testine Engineer gs the 4 responsibility of the test engineer to (1) provide the nece'ssary test equipment, (2) ensure the correct interconnection of the test equipment, (3) perform the test.

(4) document the derived data, (5) enter the test records in the appropriate project files.

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Reiss00N W ~ PROCEDURE NO. E!P-37 1 -

P.t e g 5 og 16

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, (6) be trained tw ' level II or III per E! EP 8-3, and (7) notify the QC Department of pending test. ..

t .,2 Guality Centro 1 Reoresentative It is the responsibility of the quality control representative to i

! (1) verify the test is conducted per the procedure, .

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i (1) verify data taken, (3) verify that all equipment requiring a current calibration has a

current and valid calibration sticker or certificate, i (4) verify proper disposition and storage of test records, i

l (5) obtain and maintain the test record copy of the procedure, data i sheets, and all applicable drawings, and (6) verify qualification of test engineer per EP 8-3. .

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1 3.0 REFERENCE DOCUMENTS Complete Attacheent 1 for the applicable plant-specific reference docu.

ments. As a guide, this reference should include the E! applicable program plan (s)', test plan (s), test procedure (s), and drawings.

4.0 Tf57 EQUIPMENT REQUIRED Complete Attachment I for the applicable plant-specific test equipment. As a 'gefde, this If st of test equipment should include input and monitoring instrumentation. The calibration date for monitoring instruments requiring ,

l current calibration will be recorded in Attachment 2.

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I 5.0 TEST PROCEDURE 5.1 Pretest .

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. (1) Verify that the system is configured and assembled according to the appropriate drawings deff aed in Attachment 1. This step should be accomplished at the supervision of the cognizant i engineer.

(2) perform an electrical hipot test on the system as defined in EIP-

14. Record the results in the data sheets provided in EIP-14.

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(3) Load the analog and digital isolator modules for delivery to the -

j customer into the isolator chassis, which is installed in the j cabinet.

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3 (4) Record the identity of the isolators in data sheet #1.

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l (5) Add the type-tested modules to the isolator chassis.

5.2 Test Setuo (Functional and Input Fault Test) Ref. Figure 1 ,,

Note: This test is to be performed with both A/C and D/C fault levels. Reference Table 1 for fault levels. ,

t (1) Set up the system as shown in Figure 1.

(2) Connect the analog and digital simulator outputs to the input of  ;

the type-tested modules and a set of representative deliverable modules. Follow the steps defined below. ,

27ti navisson wo. PROCEDURE NO. EIP-37 .

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Note: prior to connecting fault inputs verify correct voltage and deenergize fault source.

(3) Connect fault inputs to one of four input channels of the type-

, tested analog input via the teminal block in the cabinet.

(4) Connect a range of nomal voltage to the three remaining input ,

channels of the analog module. (See data sheet #1 for range of voltage.)

45) Connect fault inputs to one of eight input channels of the type-l tested digital input via the' terminal block in the cabinet. See note above.

, (6) Connect a range of nomal voltage inputs to the seven remaining i

channels of the digital module via a switch such that an on/off l status can be verified. (See data sheet #1 for the range of voltage.)

i (7) Connect a range of normal inputs voltage to two or three deliver-l able analog modules, depending on available output channels on ,

the simulator. (See data sheet #1 for the range of voltage.)

(4) Connect a range of normal voltages via switches on the simulator to one or two deliverable digital modules, depending on avail-ability of channels remaining on tN simulator. (See data sheet

1. 1.)

5.3 Functional and Input Fault Test Procedure Note: Use data sheet #2.

(1) Turn on the power source to the main input of the system (cabinet assembly).

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REVISWN NO, PROCEDURE NO. E!P-37 -

1 PAGE 9 0F 16

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j (2) Turn on the possir source to the analog / digital simulator and j ,

perfom a tuo point functional test of those channels connected to the simulators and record as protest data. -

. (3) Turn en the fault power source and probe each corresponding output and the power supply input at the mar of the power supply t chassis with,a digital voltmeter (DVM). Record the results in data sheets #2 as interim test data. .

Note: perfom a functional test on those channels connected to the simulators and record as post test data. If the fault condition applied to the input side of the modules creates a malfunction (see acceptance criteria), remove the j affected type-tested module and perfom a Hi-pot to verify whether or not the degradation was a result of isolation .

breakdown.

l (4) Turn off'the power source to the simulator and fault source.

i (5) Turn bff the power source to the cabinet. Repeat entire section l for remaining fault input. ,

5.4 Test Setus (Functional and Output Fault Test)

Reference Figure 2 l (1) Disconnect the applied faults to the input channel, paragraph 5.2 (3), and connect the fault for the output to the output side of l the type-tested analog module.

(2) Disconnect the applied faults to the input channel, paragraph 5.2

, (5), and connect the faults for the output to the output side of '

the type-tested digital module.  ;

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l (3) Verify,the inputs defined in 5.2 (4), 5.2 (6), 5.2 (7)', and 5.2  ;

(8) by probing the inputs at the teminal block. Use a DVM. pg

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(4) Connect a voltage calibrator to the recorder inputs and record 0-10V in 105 steps. Label the recording *0-10V calibration" and retain as part of the test record. ..

. (5) Connect the strip chart recorders to the inputs of the channels i being tested. The recorders should be set for an input range of

, = 0-10V.

5.5 Functional and Output Fault Test Procedure Note: Use data sheet #3.

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(1) Repeat steps 5.3 (1) and 5.3 (2).

(2) Start the recorders. .

(3) Turn on the fault power source and monitor each corresponding

! input of the output to which the fault condition is applied wi*h j ,

a strip chart recorder. probe each output for which a normal j input voltage is applied. Also, probe the power source input

-line at the rear of the power supply chassis. Record the results ,

in data sheets #3 as interim test data.

l Note: Perform a posttest functional as in 5.3.

(4) Repeat steps 5.3 (4) and turn off power to the cabinet.

6.0 POWER SOURCE INPUT FAULT TESTING 6.1 Setup (1) Set up the subsystem as shown in Figure 3.

Note: Remove all isolator cards except the non-deliverable type tested oncs. 281 navassoN NO. -

PROCEDURE NO. EIP-37 1 PAGE 12 or 16

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(2) Connect a range if normal voltage to the input channels of the

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analog and digital isolator module via a terutnal block. (see

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data sheet M for the range of voltage.) -

.,(3) Connect the fault input to the chassis power supply input via the PSI plug at the rear of the chassis (see Figure 3).

6.2 Functional and Power Source Fault Test Procedure Note: Use data sheet M.

(1) Turn on the power source to the analog / digital simulator.

(2) Turn on the applied fault generator.

i (3) probe each input and output of the isolator wfth DVM. Record the results in data sheet #4 as interie test data.

, Note: perform a functional test on the installed cards. If the j fault condition applied creates a malfunction (see.

acceptance criteria), then remove the modules and perform ,

a Hi-pot to verify whether or not isolation degradation has occurred. Record data on data sheet as posttest data.

7.0 ACCEPTANCE CRITERIA

! Table 1 presents the general guide for the applied faults, variables moni-i tored, and acceptance criteria summary. The applied faults must be plant j specific. Therefore, spec'ify these data when a plant-specific test is required. Where specific requirements are not imposed, output deviation from input signal shall exceed i 105.

28.3 REVISION No- . PROCEDURE NO. EIP-37 1

PAGE 14 0F 16 i

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~ 4.0 POSTTEST INSPECTION Visually inspect and verify that no damage has been caused duri'ng the test. Verify that all type-tested modules are removed from the cabinet assembly and deliverable cards are reinstalled. Perfons a 1005 two point functional test on all isolator channels and record inspection and test data on data sheet,M.

l g.0 FINAL REVIEW .

All applicable steps of this pedure have been performed as written and all signatures and other verifications are complete.

Test Engineer Signature L, _

Date /~/OCTBC, 15 Representative Signaturff%_ Date a o os.4 h

' Qualification level of test engineer verified to level II or III per EP S-3. -

Functional Manager Signatu Dite N/2t24h Test procedure approved for use.

project Manager Signature Ode _ 4! # -

Datefo/2c[dh L

281

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REVISION NO' ~ PROCEDURE NO. EIP-37 l 1 PAGE 15 0F 16

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TABLE 1 APPLIED FAULT, MNITORING, AND ACCEPTANCE CRITERIA S MiARY Applied Fault Monitor Acceptance Criteria

1. Inputs (a) output (s) (a) associated output Y Vac, M amp, -

does not exceed its M Hz -

normal range (b) other input (s) of (b) no effect on the multichannel device input and output of other channels of the device (c) power soun:e (c) no effect on the l power supply voltage l

2. Inputs same as above same as above str# Vde, 1# aspere

3. Output (a) other output (s) of (a) same as above .

l21 Vac, g ampere, multichannel device M Nz (b) input (s) (b) no effect on the

_ _ _ . . _ . . . . . . input' and output of Other channels of the device (c) power supply (c) no effect on the I Power supply l

4. power Source (a) input (s) (a) voltage on any (2g #ac, g ampere, channel does not  !

QHz ,

exceed its normal range -

i l (b) output (s) (b) same as (a) I t 28 a.

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Attachment 4 EIP-TR013: Energy Incorporated Test Report on Eight-Channel Digital Isolator Ll/NRC/ae

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