ML20212M420

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Rev 1 to Procedure STP-704, Test Procedure for Performance & Isolation Testing of 1E Analog & Digital Isolators
ML20212M420
Person / Time
Site: South Texas  STP Nuclear Operating Company icon.png
Issue date: 10/24/1986
From:
ENERGY, INC.
To:
Shared Package
ML20212M416 List:
References
ST-HL-AE-1917, STP-704, NUDOCS 8703120013
Download: ML20212M420 (33)
v • d • e


Text

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. PnOceDune DESCRIPTION ,

. TEST PROCEDURE FOR PERFORMANCE AND ISOLATION TESTING 0F 1E ANALOG AND DIGITAL ISOLATORS DATE -

"'" " '* /l kNlb CONTRACT NO.

REVIEWED BY d_j$Gj,#i',3 b) >J - E/nhy ' '8'

- REtEASE o4TE QUALITY ASSURANCE ,

o NI. ev PREPARED FOR

/ / S Texas P M ad PROJECT MANAGER As/MAftJ u s r. r e . , h - .

Y N/n/W

/

REVISIONS NOTE: All revisions are flagged with the symbol b in the right margin where N is the number of the revision.

Rev. 0 - Issued for Use - 10/30/84 Rev. 1 - Incorporated SDR STP-043 - 2/27/85 g ,p' g ( , /]f.

0703120013 870219 8 DR ADOCK 0500

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FOR INFORMATION~0NLY ISSUE DATE 00T2*1300 REVISION NO. PROCEDURE NO. STP-704 Joe coot- 5/N PAGE I OF 33

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. TABLE OF' CONTENTS .

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, PAGE 1.0 PURP0SE................................................. .......... 6 2.0 RESP 0 NS I B I L ITI ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Tes t E n g i n ee r . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Qual i ty Control Representati ve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.0 R E FER E NCE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Requi red De c.une nt s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Ot he r Re ferences . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

' 3.3 Test P rocedu re Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 j 3.4 ' Proced ure Document ati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.0 TEST EQUIPMENT REQUIRED........................*...................

9 5.0 TEST SIGNAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.0 SAFETY REQU IR EME NTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

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'"1.~0~ PRETEST.~;.~........................................................ 10 8.0 TEST PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8.1 Di gi t al Isol ato r Fun cti on al Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2 Anal og Isol ator Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 HI-Pote nti al Test ( DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 HI-Potenti al Test ( AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 Surge Withstand Capability Test............................. 15

. 8.6 Anal og Isol ato r The rwal Dri f t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.7 Anal og Isol ato r Li ne ari ty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 Anal og Isol ator Powe r Su pply Dri f t. . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.9 Analog Isolator Interchannel Effects at Saturation.......... 20 REvlsioN NO. PROCEDURE NO. sTp.704

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f TABLE OF CONTENTS (continued)

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PAGE 8.10 Anal og Isol ato r Fail ure Mode Isol ati on . . . . . . . . . . . . . . . . . . . . . . 20 8.11 Anal og Isol ator 8andwi dth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.0 P0STTE ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 10.0 ACCEPTANCE CRITERIA............................................... 23 11.0 RETEST............................................................ 24 12.0 FINAL REVIEW...................................................... 25 I

.15 REvlslON NO. PROCEDURE NO. Srp.704 1 NE 3

  1. 33 EI-14 rom .4. r.A hilmm imiims mulim il i minim m

LIST OF FIGURES .

FIGURE -

TITLE PAGE 1

Tes t Con n ecto r. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2 Digital Isolator Functional Test Configuration.............. 27 3 Digital Isolator Isolation Test Configuration............... 28 4 Analog Isolator Fune.tional Test Configuration............... 29 5 Analog Isolator Isolation Test Configuration................ 30 6 Surge Withstand Transverse Mode Test Configuration.......... 31

. 7 Surge Withster.d Connon Mode Test Configuration.'............. 32 8 Ba ndwi dth Test Con fi gu rati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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LIST OF ATTACHMENTS ATTACHMENT TITLE .

1, TEST PROCEDURES TO BE USED (2 pages) 2 TEST EQUIPENT USE LOG 3 BURN IN 4 DIGITAL ISOLATOR FUNCTIONAL TEST 5 , MOT USED .

6A NOT USED 68 NOT USED 6C ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -3, -58 60 ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -4, -56 6E NOT USED 6F NOT USED 6G NOT USED 6H NOT USED 6J NOT USED 6K NOT USED -

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6L NOT USED 7A DIGITAL ISOLATOR HI-POTEMTIAL TEST (DC) .

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78 ANALOG ISOLATOR HI-POTENTIAL TEST (DC)

,, 8A DIGITAL ISOLATOR HI-POTENTIAL TEST (AC) 88 ANALOG ISOLATOR HI-POTENTIAL TEST (AC) 9 NOT USED 10 ANALOG ISOLATOR THERHAL DRIFT (3 PAGES) 11 ANALOG ISOLATOR LINEARITY 12 ANALOG ISOLATOR POWER SUPPLY DRIFT (2 PAGES) 13 ANALOG ISOLATOR INTERCHANNEL EFFECT AT SATURATION 14 ANALOG ISOLATOR FAILURE PODE ISOLATION 15 . ANALOG ISOLATOR BANDWIDTH

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.- 1.0 PURPOSE .

This procedure provides a document verifying the performance and electrical isolation of.. Class 1E analog and digital isolators.

Transient voltages usually are capacitively or magnetically coupled from a

high voltage source o'f electrical noise into secondary circuits or control

. wiring. Since these voltages may appear unsuppressed across connection points 'of components associated with the protective system, it must be determined that they will not cause a failure or a misoperation of the system.

2.0 RESPONS!RILITIES 2.1 Testing Engineer It is the responsibility of the test engineer to:

(1) Provide the necessary test' equipment.

(2) Ensure the correct interconnection of the test equipment. .

e (3) Perform the test.

(4) Document the derived data. .

(5) Enter the test records in the appropriate project files.

(6) Be trained to level II or III per El EP 8-3. b

. (7) Notify the QC department of the pending test.

.Id l Revision NO- ' PROCEDURE NO. STP-704 I 1 PAGE 6 W 33 -

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2.2 Quality Control Representative -

It is the responsibility of the quality control representative ,to:

(1) Verify test is conducted per the procedure.

(2) Verify data taken.

(3) Verify all equipment used has a current and valid calibration '

sticker or certificate.

(4) Verify proper disposition and stor~ age of test records.

(5) Obtain and maintain the test record copy of the procedure, data sheets, and all applicable drawings. .

1 I 3.0 REFERENCE DOCUMENTS l .

! 3.1 Required Documents 1 .

Use the latest revision of the following documents: .

(1) EI Drawing 00798, Quad Class 1E Analog Isolation Amplifier Assembly.

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(2) EI Drawing 00796, Class 1E Analog Isolation Amplifier Schematic.

(3) EI Drawing 01026, Class 1E Digital Isolator Amplifier Assembly (4) EI Drawing 01030 Class 1E Digital Isolator Amplifier Schematic.

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REVISION NO. ' PROCEDURE NO. srp.7n4 3 PAGE 7 0F 33

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3.2 Other References (1) ,

IEEE Standard Guide, "IEEE 381-1977, Standard Criteria for Type Tests of Class 1E Modules Used in Nuclear Power Generating Stations". ,

(2) IEEE Standard Guide, "IEEE 467-1980, Standard Quality Assurance

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Program Requirements for the Design and Manufacture of Class IE -

l Instrumentatien and Electric Equipment for Nuclear Power Gener-ating Stations". .

(3) IEEE Standard Guide "IEEE 472-1974, Guide for Surge Withstand Capability (SWC) Tests (ANSI C 37.90-1978)".

3.3 Test Procedures Used -

, The tests to be used are job specific. The tests to be run will be speci-fied by,the program manager and listed with applicable attachments on

, Attachment 1. .

3.4 Procedure Documentation .

l Attachments used will (when completed) become part of the test procedure documentation." They will be incorporated into the test record copy of the test and submitted to project management for final review.

4.0 TEST EQUIPENT REQUIRED (1) Hipot Tester, Hipotronics Model 15125 or equivalent ,

i (2) Digital Multimetar (DMM), Fluke Model 8000A or equivalent (3) Dual Power Supply i 15 VDC output

! (4) 5-Volt Power Supply ['0 l

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(5) 0-150 VDC Powef Supply -

(6) Surge Transient Generator, Velonex Model 510 or equivalent

. (7) System Calibrator, Fluke 382A or equivalent

~(8) 4-Card Isolator Test Fixture -

(9) Test Connector EI (see F1gure 1) ,

(10) Isolator Frame Assembly, P/M 00645-1 or P/N 01000-1

, (11) Variac - 120 VAC (12) Test Leads as Required (13) Oscilloscope, Tektronics 465A or equivalent 2 MHz Bandwidth Minimum, with External Trigger -

(14) Function Generator, Square Wave. Exact 734 or equivalent 5.0 TEST SIGNAL CHARACTERIST}CS 5.1 Hi-Potential Isolation Test 5.1.1 Peak Voltage: 3 KVDC, for 15 seconds 5.1.2 Peak Voltage: 1.5 KVAC, 60 Hz for One Minute 5.2 Digital Isolator _ Test (1) Input voltages as specified on the data sheet.

. 21 REVISl0N NO. PROCEDURE NO. srp.7o4 1 PAGE q OF

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5.3 AnaTog Isolator Test -- .- ..

(1) Input voltages or current as specified on the appropr. late data sheet.

5.4 Surge Withstand Test (1) Peak Voltage: 2.5 KV.

(2) Frequency: 1.0 to 1.5 Miz (no adjustment).

(3) Waveshape: First half of cycle to be full peak voltage, then envelope decays to S0Y, of the crest value of the first peak in not less than six )sec f from the start of the wave'(no adjustment). *

(4) Repetition: The test wave shall be applied to the test

' specimen 60 times per second for two seconds.

(5) Source Impedance: 150 ohms.

6.0 SAFETY REQUIREMENTS e All safety precautions as noted in the operating manual of the Hipotronics hipot tester will be adhered to.

All safety precautions as noted in the operating manual of the Velonex Surge Trar.sient Generator will be adhered to.

Caution: Lethal voltage will be present during the performance of these tests. .

7.0 PRETEST 22 (1) Fabricate test connector per Figure 1 (if needed).

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(2) Remove all keys ~~from edgeboard connectors in prototype isolator frame.(ifused). .

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I (3) Record all test equipment used on Attachment 2.

(4) Connect +5 V and 115 V power to isolator frame per Figure 1. l (5) Adj'ist the +5-V power supply for 5 V i 10 mV.

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(6) Adjust the 115-V power ' supply for 115 V t 10 mv.

l (7) Allow all parts to operate for burn-in time specified on Attach-ment 3.

(8) Record serial numbers of each group.

8.0 TEST PERFORMANCE -

l 8.1 Digital Isolator Functional Test (1) Install digital isolator cards in the isolator frame. Record the .l serial numbers of the installed cards on the data sheet (Attach-ment 4). -

1 (2) Connect a voltmeter and the calibrator to the test connector in 1 accordance with Figure 2.

(3) Turn on the 5-volt power supply.

(4) Set the calibrator voltage at 6 V i 0.05 V. Record the output

. voltage on the data sheet. ,

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l l (5) Set the cal 1 0 alor-at 45 V i 0.05 V. Record the. output voltage on the data sheet. .

(6) Ra.ise the calibrator voltage to 48 Y t 0.1 V. Record the output voltmeter reading on the data sheet.

(7) Repeat (2) through (6) for the remaining channels for outputs as listed on Figure 2.

(8) Repeat steps (2) through (7) for all of the cards.

8.2 Analog Isolator Functional Test (1) Record the serial numbers of the installed cards on the data sheet (Attachment 6).

(2) Connect the output of the 115-V power supply to the test connec-tor per Figure 1.

(3) Turn on the 115-V power supply to the isolator frame and allow 10 minutes for warmup. .

(4) Connect the test connectors to appropriate JI- and J0- connectors p on the isolator frame.

(5) Turn on the system calibrator and adjust the output for " INPUT

. LOW" as specified.on the data sheet 20.1%. .

(6) Adjust the "zero" potentiometers on cards 1 and 2 for " OUTPUT LOW" as specified on the data sheet 20.1% on channels 1 through 4 of each card.

(7) Adjust the system calibrator output for " INPUT HIGH" .as specifled on the data sheet to.1%.

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(8) Adjust the ." GAIN" potentiometers on cards 1 and 2 for " OUTPUT HIGH", as specified on the data sheet 10.1% on channels 1 through 4 of each card. .

(9) Repeat steps (5) through (8) as required, to verify that both -

adjustments will reach their final desired values. '_

(1,0) Record the output data on the data sheet.

(11) Turn off the duhl power supply. .

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8.3 31-Potential Test (DC)

CAUTION: Lethal voltage will be present during the performance of the _

following steps: =:

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(1) Record the serial numbers of the installed cards on the data sheet (Attachment 7). h (2) Connect the Hipot Tester to all channels of both cards per Figure -[

3 (for digital isolators) or Figure 5 (for analog isolators.) ,

E (3) Turn on the Hipot Tester and set the " Raise Voltage" control to

0. I (4) Set up the Hipot Tester per the characteristics specified in I 5.1.1. .

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(5) Gradually increase the voltage applied to the isolator. T-(6) Stop increasing the voltage when 3 KV is reached or the isolator ,

y breaks down. A-I (7) Record the leakage current on the data sheet.

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4 (8) Turn off the Hipot. Tester. .

(9) Repeat (1) through (8) for the remaining cards connecting the test connectors to JI2 and J02, JI3 and J03, etc., as required.

8.4 Hi-Potential Test (AC)

CAUTION: Lethal voltage will be present during the performance of the following' steps:

(1) Record the serial numbers of the installed cards on the data -

sheet (Attachment 8).

(2) Connect the'Hipot Tester to all channels of one of the cards per Figure 3 (fo'r digital cards) or Figure 5 (for analog cards).

(3) Turn on the Hipot Tester and set the " Raise Voltage" control to

0. '

(4) Set up the Hipot Tester per the characteristics specified in 5.1.2. '

(5) Gradually increase the voltage applied to the isolator.

(6) Stop increasing the voltage when 1.5 KVAC is reached or the isolator breaks down.

(7) Let the test run for one minute.

(8) Record the leakage current on the data sheet. 1 (9) Turn off the Hipot Tester. b' (10) Repeat (1) through (9) for the remaining cards by connecting the test connectors to JI2 and J02, JI3 and J03, etc., as required.

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m 8.5 Surb Withstand Capability Test .

8.5.1 Protest Setup *

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(1) Plug the Surge Transient Generator and Oscilloscope into a 115-V,

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60-Hz source. Activate the power switch on each.

(2) Configure the scope for external trigger.

(3) Connect the SCOPE TRIGGER output of the Velonex 510 to the exter-nel trigger input of the oscilloscope per Figure 6.

(4) Connect the OUTPUT ENITOR of the Velonex 510 to the scope chan-nel 1 input.

(5)* Monitor the voltage on the 1 volt /div. scale.

NOTE: The ENITOR DUTP.UT of the Velonex 510 presents a 1000:1 attenuated output for scope monitoring.,

(6) With no output leads attached, configure the Velonex 510 as ,

follows: .

BURST EDE - Line freq.

DUTPUT TIMER MODE - Continuous (for voltage adjustment only)

DUTPUT AWLITUDE - min.

SOURCE IW EDANCE - 150 o Caution: The following steps will produce lethal voltages on the

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outputs of the Velonex 510.

2i REVISION NO. PROCEDURE NO. STP-704 1 PAGE 15 0F 33

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(7) With no load connected to the output, simultaneously. depress both HV-0N buttons. ,

.(3) Adjust the AW LITUDE of the Velonex 510 until 2.5-V peak (2.5-KV output) is displayed on the oscilloscope.

, (9) Verify that the waveshape displayed has the following character-istics. Record verification on the data sheet ( Attachment 9):

. Peak Amplitude - 2.5 KV peak Frequency - 1.0 to 1.5 MHz Fall Time - > 6 y see to fall to 50% of peak.

(10) Press either HV-ON push button to place the Velonex 510 in standby.

(11) Reconfigure the Velonex 510 as follows:

OUTPUT TIER WDE - TIED OUTPUT GUTPUT TIMER DURATION - 2 sec.

(12) Reconfigure the scope as follows: .

INPUT - Alternate (alt)

CHANNEL 1 - 1 Volt / Division l CHANNEL 2 - 2 Volt / Division l

SWEEP - 2 us/ Division

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TRIGGER - External, Positive Level and Slope (13) Connect the isolator power supply to the test connector in accor-dance with Figure 1.

9A REVISION NO. P'ROCEDURE NO. STP-704 l 1 ,

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(14) Record the .sertal numbers of the cards on the data, sheet.

r (15) . Insert the cards to be tested into the test chassis. .' d it .

.(16) Forform a functional test on the selected cards per the appro-priate section of this procedure. '

t (17) Connect the Velonex 510 output leads (Caution: verify the unit is in standby) to the test connector in accordance with Figure 6.

(18) Connect Channel 2 of the oscilloscope to the test connector in accordance with Figure 6.

(19) ~ QC Representative verify all test connections and initial appro-priate column on data sheet.

8.5.2 Test Performance (20) Turn on the isolator power supply. ,

(21) Visually monitor the oscilloscope. Channel I will display the ,

applied surge wavefona. Channel 2 will verify the application of the surge wavefona to the channel being tested.

(22) Depress both HV-ON push buttons of the Velonex 510 simultaneously.

(23) Depress the START button of the Velonex 510.

(24) Document the application of the SWC Transverse Mode voltage to

. the test specimen by initialing the appropriate column. .

(25) press either of the HV-0M push buttons to place the Velonex 510 in standby.

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(26) Connect the VeTonex output leads and Channel 2 of the oscillo-scope to the test connector in accordance with Figure 7. .

-(27) Repeat steps (19) through (23).

(28) Document the application of the SWC Common Mode voltage to the test specimen by initia11ng the appropriate column on the data sheet.

(29) Press either of the ,HV-ON push buttons to place the Velonex 510 in standby.

(30) Perform a functional test on the channel per the appropriate section of this procedure. Attach a completed copy of the func-tional test data sheet with pre- and post-SWC test data.

(31) Repeat (17) through (30) for all channels on the card.

8.6 Analon Isolator Thermal Drift.

(1) Record the serial number of the card on the data sheet (Attach- ,

ment 10). .

(2) Calibrate the card according to the appropriate functional test of Section 8.2.

(3) Set the Environmental Chamber temperature to ambient. Allow card to operate for a period of 20 minutes at the set temperature.

(4) Take input and output data for high and low inputs.

(5)' Repeat steps (3) and (4) for temperatures 5'C, 10*C, 15'C, and 20'C below ambient.

(6) Return the chamber to ambient and repeat step (3). 30 -

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(7) Repeat steps (3) through (5) for temperatures 5'C.10*C,15'C, and 20*C above ambient.. .

8.7 Analog Isolator Linearity (1) Record the serial number of the card on the data sheet (Attach-ment 11).

(2) Calibrate the card according to the appropriate functional test of Section 8.2. . ,

(3) Allow card to operate at ambient temperature for 20 minutes.

(4) Take readings across the input span in increments of 25% of the span starting at the low end.

8.8 Analog Isolator power Supply Drift (1) Record the serial number of the card *on the data sheet (Attach-ment 12).

(2) Calibrate the card according to the appropriate functional test of Section 8.2. .

(3) Allow card to operate at ambient temperature for 20 minutes.

(4) Adjust the i 15-V. power supplies to i 15 VDC t 0.001 VDC.

. (5) Apply a 50% full scale input to the card using the system calibrator.

(6) Record the outputs of each channel. .

(7) Adjust the +15-VDC power supply to +15.025 + 0.001 VDC.

31 7tEVISION 'NO. ~ ~ ' ~ PROCEDURE NO. sTp-704 1 PAGE to0F 33 g7 _ ,,,

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(8) Record the outpigs af each channel. -

(9) Repeat steps (7) and (8) adjusting the + 15 VDC to '+ 15.050 VDC.

. .(10) Repeat steps (7) and (8) using +14.975 VDC.

(11) Repeat steps.(7) and (8) using +14.950 VDC.

(12) Return the +15-VDC supply to 15 VDC t .001.

(13) Repeat steps ,(7) to (11) adjusting the VDC supply to the negative values. -

8.9 Analon Isolator Interchannel Effects at Saturation (1) Record the serial number of the card on the data sheet (Attach-ment 13). ,

(2) Calibrate the card according to the appropriate functional test of Section 8.2.

(3) Apply a 50% of full scale input to all the channels. Reconi the outputs. .

(4) Continue to apply a 50% of full scale input to three channels and apply a 1255 of full scale input to the fourth. Record the outputs of all channels.

8.10 Analog Isolator Failure Mode Isolation -

(1) Record the serial number of the card on the data sheet ( Attach- ,

ment 14).

(2) Calibrate the card according to the appropriate functional test of Section 8.2. .

REVISION NO. PROCEDURE NO. sTP-704 .,

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. (3) ,

Connect a 4.7K n resistor across each of the outputs.

(4) Connect a IK resistor and DMM across the input terminals. *15 volt power is applied for all tests. Record the DC voltage at h

the inputs on the data sheet.

(5) Short across the 4.7K o resistor.

(6) Measure the DC voltage at the inputs and record on the data

. sheet.

(7) Remove the 4.7K Q resistor, measure the DC voltage at the inputs and record on the data sheet.

(8) Connect 15 VDC across tia output terminals with the polarity the same as the output. Measu're the DC voltage on the inputs and record on the data sheet.

(9) Connect 15 VDC across the output terminals with the polarity opposite the output. Measure the DC voltage on the input and record on the data sheet.

-(10) Connect 120 VAC through a 10K n. 2-watt rbsistor to the output terstnals. Measure the AC voltage on the inputs and record on the data sheet.

8.11 Analog Isolator Bandwith (1) Record the serial number of the card on the data sheet (Attach-ment 15).

(2) Calibrate the card according to the appropriate functional test -

of Section 8.2.

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(3) Apply a square wave.from the function generator with a magnitudo of 50%, to 100% of full scale input and a duration (T) calculated

.from'the equation below to the inputs of the card.

d T = 10 RC where R and C are taken from EI DWG No. 00796.

Channel R C .

1 R4 + 1/2 RS- 'C 1 ,

2 C4 R13 + III "14 3 C R22 + I/2 R23 7 4 C R31 + 1/2 R32 10 (4) Record the value of RC for the channel on the data sheet.

(5) Connect the oscilloscope and the wavefona generator as shown on Figure 8.

(6) Adjust the oscilloscope to display the output of the isolator

!' exactly between the 0% and 100% graticle lines.

(7) Adjust the sweep to display approximai;ely 5 RC.

(8) Enter on the data sheet the time taken for the output to rise from zero to the 63% line on the graticle.

(9) Repeat steps (4) through (8) for all channels on the card.

9.0 POSTTEST (1) Remove all test equipment and test leads and fixtures.

(2) Return all isolator cards to controlled storage for proper storage.

31

~ REVISION NO. PROCEDURE NO. STP-704 -

.g.. ._ ~

PAGE 22OF 33

. E. .'? 8. . . .,

., 1

.(3) Submit all data sheets and data acceptance sheets to the respon-sible engineer for review and acceptance or rejection of the tested cards. .

10.0 ACCEPTANCE CRITERIA 10.1 Digital Isolator - Functional Test t

(1) Output less than 1 volt for an input of S volts (DC for -1 ,

l assembly. AC RMS for -2 assembly). -

(2) Output greater than or equal to 3.8 volts for an input voltage of 45 volts.

~

10.2 Analog Isolator Functional Test l

(1) Outputs within 0.1% of output span for inputs at high and low limits of input span.

10.3 HI-Potential Isolation Tests (DC and AC)

(1) Leakage current less than 10 vADC at 3 KVDC. .'

f (2) Leakage current less than I a AAC ras at 1.5 KVAC.

10.4 Surge Withstand Capability Test (1) The channel fails if "zero" and/or " gain" adjustments cannot be made to bring amplifier output to witnin tolerances after SWC l test.

l (2) The channel fails if after the SWC test the output fails to l

return to within 0.1% of the output span of the pre-SWC test I l value.

36 1

--. --. REY 1Sl0N_. .No _.._ -

PROCEDURE NO. STP-704 -

1 ' PAGE 23 OF 33 in -',*,,,g 13?-1 e

10.5 Thermal Drift

  • ~~

(1) Output change of less than 0.015% of output span per.*C for the range of 10'C to 40*C. '

10.6 Linearity (1) Output variance from tracking the input is less than 0.1% of the ,

output span.

10.7 Power Supply Drift (1) Output change less than 0.15% of the output span, g

~

10.8 Interchannel Effect at Saturation (1) Output change less than 0.05% of the output span.

10.9 Failure Mode Isolation (1) Voltage change from preliminary readings at the input of less than 0.01% of input span.

g 10.10 Bandwidth (1) Measured rise time (t) less than or no more than 20% greater than b

calculated RC. ,

11.0 RETEST (1) Any card failing the acceptance criteria shall be returned to the ,,

card vendor for repair.

36

~~ ~

' REVISION ~ N6 ' ~ PROCEDURE NO. STP-704 ,

~~

1 PAGE 24 0F 33 f -

339,g m a sc/ W

.s

12.0 FINAL REVIEW ,

All appl.icable steps of this procedure have been performed as.' written and all signatures .and other verifications are complete.

Test Engineer Signature #; e8 Date d5%oc e n , ,

l QC Representative Signa, turd' - #f ## M n*-

5" M M .'

& kt i i

! Qualification level of test engineer, verified to level II or III. d Functional Manager Signatur /' 9 M// ate /8/52dil6

p. , , - - - -

L Test procedure approved for use.

I l

Project Manager Signature Date f

l 3i REVISION NO. PROCEDURE NO. STP-704

..p._.- -.

PAGE 250F 33 EI-146

PS

-9 ( + i 15v

' J1

. INPUT BC c rewan i s i 7( - s. veri.y 2 h3 3 >5

  • '7 5 h9 6 > 11 7 ' 13 2< + IV 8 C 15 g/' rowan , C 2 '

SUPPL.Y (4

18 h (e is

~ >8 73 ' 10 JO OUTPUT ia <

C iz 65 gq-s '

I' e 46 ' 16

2. > 2 ,7 C 97 3g 3 T $55 4 < tt > 53 5 - 5 zo ' st b ) b 7

21

( 497 7g 'C T *2 23 ( "45 9C 20 (,

to 24 (-x 43

  • ZI > 11
  • gg ( gg 26 54 22 k  !.E 27 h 52 23- 13 sq AMP CONNECTOR PARTS NEEDED 28 '(sogg 29 > g 2F) 15 3o 46 1(,) 16 Pl.UG PART AMP No. 3, j qq 87 27'c- PS Plug 206708-1 32. > 4 2.

28 e 88 Cable Clamp 206966-1 (5) Socket 205090-1 or 66602-1 JO Plug 205839-3 Cable Clamp 206070-1 (18) Socket 205090-1 or 66602-1 JI Plug 206437-1 Cable Clamp 206512-1 (32) Pin 205089-1 o

- - - . - . . ._. ~

0 "a FIGURE 1

~~

Test Connector en w - -- . , - -

N

, . .~

f .

. INPUT i

SYSTEM E. 2

'. CALIBR ATOR e ..as-o 3 c ,.. x oR 5

VARIAC ,.e i.36-s) [- 6 p u

- 8 9

. .!2 it is 63

~

19 OUTPUT gg l 16 1 _ 17 3 7 4 (9 I to b ti 7 22 23 9

8' 24 25 ii 25 4-t a6 ee

  • g,

- -is DMM so 38 l'

17 g 88 OUTPUT TEST CONNECTIONS 000 CARD EVEN CARD CHANNEL 2 17 1

4 15 2 13 3 6 8 11 4

1 18 5

3 16 6

5 14 7

7 12

... . . . - 8 10 9

Com ,J o

FIGURE 2 Digital Isolator Functional . Test Configuration STP-704 ... ,, ,,,e ,,

-~

. '(NPUT

~

HIPOT TESTER D C At 3.0 AV f.5 K v , 3 A c 'av 4

Low GHD HIGH 5 O O O '

7 ODD CARD 8 HIG H -

9 10 y 11 '

1 4

To IS O L ATOR FRAME t3

'M OUTPUT

'I

  • s ODD CARD EVEN 16 2

3 Low CARD 17 HIGH - T 19 5

g to 2

7 22 T .

23 9

to .

EVEN 25 CARD -

26 1 LOW 27

'3 28

-- 1 84 29

~

. . 30 I'

3 88 DC Test may be conducted on both cards simultaneously.

AC Test to be run on one card at a time.

l -

~~

FIGURE 3 l Digital Isolator Isolation Test Configuration .j ()

STP-704

. Page 28 of 33

<t

.e ^

INPUT' E '

. SYSTEM z

~

3 CALiBRATER E

  • J-G 7

+ 50

  • ll 81 Y-CUTPUT l

$ lf

' 86 17 T

19 to 6 11 7 22 7 23 24 .

iO Ii

-gr ee xse E 29

'5 t6 I) MM so l

~~

. 2.

R TEST CONNECTIONS CHANNEL 000 CARD EVEN CARD INPUT OUTPUT INPUT OUTPUT

. (+) (-) '(+) (-) (+) (-) (+) (-)

~

1 13 16 8 7 29 32 ' 11 12 .

2 5 8 6 5 21 24 13 14 3 9 12 4 3 25 28 15 16 4 1 4 2 1 17 20 17 18 l

be connected in serie f wh e vo oop tageinputs inputs naly u be connected in parafleir simultaneous adjustment l

! *Cudent .

FIGURE 4 Analog Isolator Functional Test Configuration' *1I 7N n.., ,o ,,, ,,

i tl

. .~ .

4, .

_ .' INPUT HIPOT TESTER se a a.o uv 2

. AC e 3.s sty 3 4

LOW 6ND Hl8H 5 OOO T 8

OAS to HIG N H

- y it.

opp TO ISO LATO R FR AM E i3 OUTPUT CARD Low 19 I 15 2, 16 3

EVE" -

U g

CARD 7 HI6H l

5 19

(, to 7 2 T

  • 22 g _

23 88 EVEN 8_ .

In CARD

  • 25 low "Ag .

83 EL 4 28_

[. I5 _M 30 I6 l :7 33

~~

l --

rg 31

- - DC Test may be conducted on both cards simultaneously.

l XC Test to be run on one card at a time.

1 l

i FIGURE S -

Analog Isolator Isolation Test Configuration STP-704 .

Pace 30 of 33 o

. INPUT g

HIG H Q S WG -TE S.TE'R -!-

Low C ,_

e4oN.- $YNC 5 O O- 'T -

!. y .

8 9

to it

. it i3 19 OUT'PUT

. , is h gs

z y l' 3 T i
  • q i'

s zo

5 ,

zi

. 7 22 T 23

! 9

,. 2 s -

ii o ca. I osvac ,

as 26 g 2' i3 ca.2 SCOPE 28

( - in O 29 IS 3 8' (Analog Channel Shown) 3I

~ 17 DIGITAL ISOLATOR 32.

CHANNEL ODD CARD EVEN CARD

(+)IN(-) OUTPUT (+)1N(-) OUTPUT I 17 25 17 t

1 1 9 2 2 2 10 4 18 26 15 '

3 3 11 6 19 27 13 4 4 12 8 20 28 11 nalog Isolator 1 puts and Outputs 6 6 j

isted en Figure 7. 7 7 15 5 23 31 14 8 8 16 7 24 32 12 Com 9 10 .ld ,

FIGURE 6 Surge Withstand Capability Transverse Mode Test Configuration ,

r M

~

~

(NPUT HIG H C Ih i

SWC TESTCR owc j; ,

McN- SYNC 5 O O c 1

8 .

t l- to_ -

l n

b d I" OUTPUT E, 'S

. , gs [

A se r 1 U gy [

- g-3

" 19 to 2n 22 7 23 24 .

to 25 ii O Osvac .

26 cw. s 2'

.- t,, -

ca a o SCOPE 29

' 30 (Analog Channel Shown) 31

_. . . . . . _ . _ g ANALOG ISOLATOR 1 ODO CARD EVEN CARD CHANNEL

..x

.=. _. ' (+)1N(-) (+)0UT(-) (+)IN(-) (+)00T(-)

13 16 8 7 29 32 11 12 1

Digital Isolate

  • 2 5 8 6 5 21 24 13 14 Inputs and 3 9 12 4 3 25 28 15 16 Outputs listed 4 2 1 17 20 17 18 4 1 en Figure 6.

FIGURE 7 Surge Withstand Capability Common Mode Test Configuration.

STP-704 Page '32 of 33 l 3L

, s s

? IN PUT' 6 2 5

' WAVEFORM -

--c3 3 GENERATOR g , .

s G

7 8

1 to il 11 83 19 OUTPUT is

. , ['

j d O 'avr s?ac T

a SCOPE i, to g

21 7

22 T 23 9 29 to 8 8 0 % - - - - - .- - - - - - - - - - - - - -  ! '

I 2I It I *'

83._  ! l 27 13

9

'3 5 - - - -* - * - ~ ~ ~ l - - - - - - - - - - l- - - . . ) 28 3

1' is l 1 30 is  : 1 1 3'

av l l l 31 18 0% .-----l------------------t

.. _. . . . . . _ _ . _ . . _ _ . ytq "

l i; SRC ..

See Figure 4 for Test Connections Table 9 -

ia FIGURE 8 Analog Isolator Bandwidth Test Configuration 9

- - - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

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