ML20212M425
| ML20212M425 | |
| Person / Time | |
|---|---|
| Site: | South Texas  |
| Issue date: | 10/24/1986 |
| From: | ENERGY, INC. |
| To: | |
| Shared Package | |
| ML20212M416 | List: |
| References | |
| EIP-24-01, EIP-24-1, NUDOCS 8703120015 | |
| Download: ML20212M425 (34) | |
Text
__
s Q.. l mRGY INCORPORAM PROCEDURE DESCRIPTM TEST PROCEDURE FOR PERF0lNUICE AND ISOLATION TESTING OF 1E ANALOG AND DIGITAL ISOLATORS
( Ao D l F t E.D)
F, s-w4
'CL S-2SJL DATE e.
./
8'#8 CONTRACT NO.
M pagPARED BY' REVIEWED BY WC 4
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RELEASE DATE '
QUALITY ASSURANCE Wb d b'
- ~3/-W PREPARED FOR
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A "lL - -
- '* 'T PROJECT MANAGER Lws(, f fisTf*g.
?u REVISIONS All revisions are flagged with the symbol b in that.right margin NOTE:
where N is the number of the revision.
Rev. 0 - Issued for Use - 8/31/84 e en.. em Bi>B"$EN'On" FORINFORMATION ONLY I
msusout DCT 241986 -
lo REvesmN NO.
PROCEDURE NO.
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JOS CODE-S/N PAGE OF tv.157 2 o
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..... TABLE OF CONTENTS PAGE 1.0 PURP0SE............................................................
6 2.0 RESP 0NSI B I LITIES................................................... 6 2.1 Tes t E ngi neer................................................ 6 2.2 Qual i ty Control Representative............................... 7 3.0 REFERENCE D0CUIENTS................................................ 7 3.1 Requi red Docume nts........................................... 7 3.'2.
Othe r Re feeences............................................. 8 3.i3 Tes t Procedure Use.......................................... 8
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3.4 Procedure Documentati on..................'................... 8 4.0 TEST EQUIPMENT REQUIRED............................................
9 5.0 TEST SIGNAL CHARACTERISTICS..................................... 9_.._.
6.0 SAFETY REQUIREMENTS...............................................
10
- 7. 0 PRdE5a r........................................................ 10 8.0 TEST PE RFORMANCE.................................................. 11 8.1 Di gi tal Isol ator Functional Test............................ 11 8.2 Anal og Isol ator Functi onal Test............................. 12 8.3 HI-Potenti al Test ( DC)...................................... 13 8.4 HI-Potenti al Test ( AC)...................................... 14 8.5 Surge Wi thstana Capabili ty Test..........'................... 15 8.6 Anal og Isol ato r Thensal Dri ft............................... 18 8.7, Anal og Isol ator Lineari ty................................... 19l 8.8 Anal og Isol ator Power Supply Dri ft..........................'.1Y 8.9 Analog Isolator Interchannel Effects at Saturation.......... 20 REVISIOlt NO~ ~ PROCEDURE NO.
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TABLE OF CONTENTS (continued)
PAGE 8.10 Anal og I sol ato r Fail ure Mode Isol ati on...................... 20
- 8.11 Anal og Isol ator Bandwi dth................................... 21
- 9. 0' P0STTEST.......................................................... 22 10.0 ACCEPTANCE CRITERIA............................................... 23 11.0 RETEST............................................................
24 I
i 12.0 F I N AL REV IEW...................................................... 2 5 l
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PROCEDURE NO.
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... ~ LIST OF FIGURES FIGURE TITLE PAGE
,p 1,
Tes t Connector.............................................. 26 2
Digital Isolator Functional Test Configuration.............. 27 3
Digital Isolator Isolation Test Configuration............... 28 4
Analog Isolator Functional Test Configuration............... 29 5
Analog Isolator Isolation Test Configuration................ 30 6
Surge Withstand Transverse Mode Test Configuration.......... 31 7
Surge Withstand Common Mode Test Configuration.............. 32 8
Bandwi dth Test Confi guration................................ 33 5
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. _. LIST OF ATTACHMENTS ATTACHMENT TITLE 1
TEST PROCEDURES TO BE USED 2~
TEST EQUIPMENT USE LOG 3
BURN IN 4
DIGITAL ISOLATOR FUNCTIONAL TEST 5
NOT USED 6A ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -1, -51, -60 68 ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -2, -52 6C ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -3, -58 60 ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -4, -56 6E ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -5 6F ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -6 6G i
ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -7 6H ANALOG ISOLATOR PJNCTIONAL TEST ASSEMBLY -8 '
6J
' ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -9 6K ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -10 6L ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -53 7A DIGITAL ISOLATOR HI-POTENTIAL TEST (DC) 7B ANALOG ISOLATOR HI-POTENTIAL TEST (DC)
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SA DIGITAL ISOLATOR.HI-P0TENTI.AL TEST (AC) 88 ANALOG ISOLATOR HI-POTENTIAL TEST (AC) 9 SURGE WITHSTAND CAPABILITY TEST 10 ANALOG ISOLATOR THERMAL DRIFT (3 PAGES) 11 ANALOG ISOLATOR LINEARITY
.12 ANALOG ISOLATOR POWER SUPPLY DRIFT (2 PAGES) 13 ANALOG ISOLATOR INTERCHANNEL EFFECT AT SATURATION 14 ANALOG ISOLATOR FAILURE MODE ISOLATION 15 ANALOG ISOLATOR BANDWIDTH 5
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4 1.0. PURPOSE This procedure provides a document verifying the performance and electrical isolation of Class IE analog and digital isolators.
I Transient voltages usually are capacitively or magnetically coupled from a high voltage source of electrical noise into secondary circuits or control wiring.
Since these voltages may appear unsuppressed across connection i
l points of components associated with the protective system, it must be l
determined that they will not cause a failure or a misoperation of the system.
2.0 RESPONSIBILITIES Il l
2.1 Testing Engineer It is the responsibility of the test engineer to:
l a
(1)
Provide the necessary test equipment.
(2)
Ensure the correct interconnection of the test equipment.
(3)
Perfom the test.
(4)
Document the derived data.
l (5)
Enter the test records in the appropriate project files.
l (6)
Se trained to level II or III per EI QAP 10-2.
-(7)
Notify the QC department of the pending test.
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sa 2.2 Quality Control ihrpresentative It is thi responsibility of the quality control representative to:
e (1)
Verify test 17. conducted per the procedure.
(2)
Verify data taken.
(3)
Verify all equipment used has a current and valid calibration sticker or certificate.
(4)i Verify proper disposition and storage of test records.
(5)' Obtain and maintain the test record copy of the procedure, data sheets, and all applicable drawings. ' -
3.0 REFERENCE DOCLMENTS 3.1 Required Documents Use the latest revision of the following documents:
(1)
EI Drawing 00798, Quad Class 1E Analog Isolation Amplifier Assembly.
(2)
EI Drawing 00796, Class 1E Analog Isolation Amplifier Schematic.
(3)
EI Drawing 01026. Class 1E Digital Isolator Amplifier Assembly (4)
EI Drawing 01030, Class 1E Digital Isolator' Amplifier Schematic.
ti Ti2
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3.2 Other References (1)
IEEE Standard Guide, "IEEE 381-1977, Standard Criteria'for Type Tests of Class 1E Modules Used in Nuclear Power Generating Stations".
(2)
IEEE Standard Guide, "IEEE 467-1980, Standard Quality Assurance Program Requirements for the Design and Manufacture of Class 1E Instrumentation and Electric Equipment for Nuclear Power Gener-ating Stations".
(3)
IEEE Standard Guide, "IEEE 472-1974 Guide for Surge Withstand
! Capability (SWC) Tests (ANSI C 37.90-1978)".
I 3.3 Test Procedures Used i
The tests jto be used are job specific.. The tests to be run will be speci-fled by the program manager and listed with applicable attachments on Attachment,1.
3.4 Procedure Documentation Attachments used will (when completed) become part o' the test procedure dociamentation. They will be incorporated into the test record copy of the test and submitted to project management for final review.
I 4.0 TEST EQUIPMENT REQUIRED (1)
Hipot Tester, Hipotronics Model HD125 or equivalent
- (2)
Digital Multimeter (DMM), Fluke 2 del 8000A or equivalent I
li (3)
Dual Power Supply i 15 VDC output fi.i (4) 5-Volt Power Supply
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(5) 0-150 VDC Power Supply (6) Surge Transie'nt Generator, Velonex Model 510 or_equiva, lent (7) System Calibrator, Fluke 382A or equivalent (8) 4-Card Isolator Test Fixture (9) Test Connector, EI (see Figure 1)
-(10)
Isolator Frame _ Assembly, P/N 00645-1 or P/M 01000-1 (11)< Variac.- 120 VAC 1
(12), Test Leads as Required i
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(13)' Oscilloscope. Tektronics 465A or equivalent 2 MHz Bandwidth j
Minimum, with External Trigger (14) Function Generator, Square Wave Exact 734 or equivalent t
5.0 TEST SIGNAL CHARACTERISTICS 5.1 Hi-Potential Isolation Test 5.1.1 Peak Voltage: 3 KVDC, for 15 seconds 5.1.2 Peak Voltage:
1.5 KVAC, 60 Hz for One Minute 5.2 Digital Isolator Test (1)
Input voltages as specified on the data sheet.
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5.3 Analog Isolator Test -'
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Input voltages or current as specified on the appropriate data sheet.
5.4 Surge Withstand Test
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(1),Ppak Voltage:
2.5 KY.
(2)
Frequency:
1.0 to 1.5 MHz (no adjustment).
(3) 'Waveshape:
First half of cycle to be full peak voltage, then envelope decays to 50% of the crest value
(
of the first peak in not,less than six usec from.the start of the wave (no adjustment).
(4)
Repetition:
The test wave shall be applied to the test specimen 60 times per second for two seconds.
(5).Source Impedance:
150 ohms.
6.0 SAFETY REQUIREMENTS All safety precautions as noted in the operating manual of the Hipotronics hipot tester will be adhered to.
All safety precautions as noted in the operating manual of the Velonex Surge Transient Generator will be adhered to.
ggggg:
Lethal voltage will be present during the performance of these tests.
r 7.0 PRETEST (1)
Fabricate test connector per Figure 1 (if needed).
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(2). Remove all keys from edgeboard connectors in prototype isolator 1
frame (if used).
(3)
Record all test equipment used on Attaclusent 2.
[
(4)
Connect +5 V and t15 V power to isolator frame per Figure 1.
l (5)
Adjust the +5-V power supply for 5 Y t 10 WV.
(6)
Adjust the 215-V power supply for 215 Y t 10 mV.
l (7). Allow all parts to operate for burn-in time specified on Attach-r ment 3.
k (8)" Record serial nimbers of each group.
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' 8.0 TEST PERFORMANCE r
i 8.1 Digital Isolator Functional Test l
(1)
Install digital isolator cards in the isolator frame.
Record the i
serial ntmbers of the installed cards on the data sheet ( Attach-ment 4).
(2)
Connect a voltmeter and the calibrator to the test connector in accordance with Figure 2.
(3)
Turn on the 5-volt power supply.
(4)
Raise the calibrator voltage until the output voltmeter reads:
1 Y t 0.05 V.
Record the calibrator output voltage on the data i
I. sheet.
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(5)- Raise the calibrator' voltage until the output voltmeter reads 3.8 Y t 0.05 Y.
Record the calibrator output voltage on the data sheet.
-(6)
Raise the calibrator voltage to 48 Y t 0.1 V.
Record the output voltmeter reading on the data sheet.
(7)
Repeat (2) through (6) for the remaining channels for outputs as listed on Figure 2.
(8)' Repeat steps (2) through (7) for all of the cards.
8.2 Analog Isolator Functional Test i
(1): Record the serial numbers of the installed cards on the data
. sheet ( Attachment 6).
(2)' Connect the output of the t15-V power supply to the test connec-f
. tor per Figure 4.
1 3
(3)
Turn on the 215-Y power supply to the isolator frame and allow 10 i
minutes for warmup.
(4)
Connect the test connectors to appropriate JI-and J0- connectors on the isolator frame.
(5)
Turn on the system calibrator and adjust the output for " INPUT LOW" as specified on the data sheet 10.15.
(6)
Adjust the "zero" potentiometers in cards 1 and 2 for " OUTPUT LCW" as specified on the data sheet 20.1% on channels 1 through 4' of each car,d.
(7)
Adjust the system calibrator output for " INPUT HIGH" as specified on the data sheet to.15.
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y (8)
Adjust the " GAIN"-potentiometers on cards 1 and 2 for output _at specified on the data sheet 20.15 on channels 1 through 4 of each card.
.(g)
Repeat steps (5) through (8) as required, to verify that both adjustments will reach their final desired values.
(10)
Record the output data on the data sheet.
(11)
Turn off the dual power supply.
8.3 Hi-Potential Test (DC)
CAUTION:
Letha1' voltage will be present during the performance of the following steps:
(1) 4tecord the serial numbers of the installed cards on the data sheet ( Attachment 7).
(2)
Connect the Hipot Tester to all channels of both cards per Figure 3 (for digital isolators) or Figure 5 (for analog isolators.)
(3)
Turn on the Hipot Tester and set the " Raise Voltage" control to 0.
(4)
Set up the Hipot Tester per the characteristics specified in 5.1.1.
(5)
Gradually increase the voltage applied to the isolator.
'(6)
Stop increasing the voltage when 3 KV is reached or the isolator breaks down.
l (7)
Record the leakage current on the data sheet.
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(8)
Turn off the Hipot Tester.
(9)
Repeat (1) through (8) for the remaining cards connecting the test connectors to Jf2 and J02, JI3 and J03, etc., as required.
8.4 Hi-Potential Test ( AC)
CAUTION: Lethal voltage will be present during the performance of the following steps:
(1)
Record the serial nebers of the installed cards on the data
(, sheet ( Attachment 8).
1 (2);' Connect the Hipot Tester to all channels of one of the cards per
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!! Figure 3 (for digital cards) or Figure 5 (for analog cards).
(3)
Turn on the Hipot Tester and set the " Raise Voltage" control to 0.*
(4)
Set up the Hipot Tester per the characteristics spec 1fied in 5.1.2.
~
(5)
Gradually increase the voltage applied to the isolator.
(6)
Stop increasing the voltage when 1.5 KVAC is reached or the
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isolator breaks down.
(7)
Let the test run for one minute.
(8)
Record the leakage current on the data sheet.
(9)
Turn off the Hipot Tester.
(10)
Repeat; (1) through (9) for the remaining cards by connecting the test connectors to JI2 and J02, JI3 and J03, etc., as required.
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8.5 Surge Withstand Capability Test 8.5.1 Protest Setup (1)
Plug the Surge Transient Generator and Oscilloscope into a 115-V, 60-Hz source.
Activate the power switch on each.
l
~(2)
Configure the scope for external trigger.
(3)
Connect the SCOPE TRIGGER output of the Velonex 510 to the exter-nal trigger input of the oscilloscope per Figure 6.
I (4)
Connect the OUTPUT MONITOR of the Velonex 510 to the scope chan-nel 1 input.-
l (5) enitor the voltage on the 1 volt /div. scale.
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The M)NITOR QUTPdT of the Velonhx 510 presents a 1000:1 Iattenuated output for scope monitoring.
~
(6)
With no output leads attached, configure the Velonex 510 as follows:
BURST MODE - Line freq.
OUTPUT TIMER MODE - Continuous (for voltage adjustment only)
OdTPUT ANLITUDE - min.
SOURCE IMPEDANCE - 150 0 Caution: The following steps will produce lethal voltages on the outputs of the Velonex 510.
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JOB CODE - S/N PAGE15 0F 33
(7)
With no load connected to the output, simultaneously depress both HV-ON buttons.
(8)
Adjust the AWLITUDE of the Velonex 510 until 2.5-V peak (2.5-KV output) is displayed on the oscilloscope.
(9)
Verify that the waveshape displayed has the following character-istics.
Record verification on the data sheet ( Attachment 9):
' Peak Amplitude - 2.5 KV peak Frequency - 1.0 to 1.5 MHz i Fall Time - > 6 y sec to fall to 50% of peak.
(10) f Press either HV-ON push button to place the Velonex 510 in standby.
(11) l Reconfigure the Velonex 510 as follows:
i l OUTPUT TIER MDDE - TIED OUTPUT GUTPUT TIMER DURATION - 2 sec.
(12)
Reconfigure the scope as follows:
INPUT - Alternate (alt)
CHANNEL 1 - 1 Volt / Division CHANNEL 2 - 2 Volt / Division SWEEP - 2 us/ Division (TRIGGER - External Positive Level and Slope (13)
Connect the isolator power supply to the test connector in accor-dance with Figure 1.
1 1.1
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(14)
Record the serial-mmbers of the cards on the data sheet.
(15)
Insert the card to be tested into the test connector.
(16)
Perform a functional test on the selected cards per the appro-priate section of this procedure.
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Oba) fu6cm e,. #;- Mrdrade,,[ Te.st (pt) a-d (AC) on th e 4,../ /4. /-X-1 (17)
Connect the Velonex 510 output leads (Caution: verify the unit is in standby) to 1!he test connector in accordance with Figure 6.
(18)
Connect Channel 2 of the oscilloscope to the test connector in
- accordance with Figure 6.
j s
(19)! QC Representative verify all test connections and initial appro-priate column on data sheet.
8.5.2 Test Performance (20)
Turn on the isolator power supply.
(21)
Visually monitor the oscilloscope.
Channel 1 d11 display the applied surge waveform.
Channel 2 will verify the application of the surge waveform to the channel being tested.
(22)
Depress both HV-ON push buttons of the Velonex 510 simultaneously.
(23)
Depress the START button of the Velonex 510.
(24)
Document the application of the SWC Transve'rse 2de voltage to the test specimen by initiating the appropriate column.
(25)
Press either of the HV-ON push buttons to place the Velonex 515 -
in standby.
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..C (26)
Connect the Velonex output leads and Channel 2 of the oscillo-scope to the test connector in accordance with Figure 7.
(27) ' Repeat steps (19) through (23).
(28)
Docuent the application of the SWC Casumon Mode voltage to the test specimen by initialing the appropriate column on the data sheet.
l (29)
Press either of the HV-ON push buttons to place the Velonex 510 in standby.
I (30)
Perform a functional test on the channel per the appropriate Isection of this procedure.
Attach a completed copy of the func-kional test data sheet with pre-and post-SWC test data.
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8.6 Analog Isolator Themal Drift (1) Record the serial number of the card on the data sheet (Attach-ment 10).
l (2)
Calibrate +,he card according to the appropriate functional test of Section 8.2.
- l (3)
Set the Environmental Chamber temperature to ambient. Allow card to operate for a period of 20 minutes at the set temperature.
(4)
Take input and output data for high and low inputs.
(5)
Repeat steps (3) and (4) for temperatures 5'C,10*C,15'C, and
'20'C below ambient.
~
(6)
Return the chamber to ambient and repeat step (3).
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(7)
Repeat steps (3) through (5) for temperatures 5'C,10*C,15*C, and 20*C above ambient.
8.7 Analog Isolator Linearity (1)
Record the serial masber of the card on the data sheet (Attach-ment 11).
(2)
Calibrate the card according to the appropriate functional test
, of Section 8.2.
(3)
Allow card to operate at ambient temperature for 20 minutes.
(4) E Take readings across the input span in increments of 25% of the
{
span starting at the low end.
8.8 Analog Isolator Power Supply Drift I
(1)
Record the serial number of the card on the data sheet (Attach-ment 12).
(2)
Calibrate the card according to the appropriate functional test of Section 8.2.
(3)
Allow card to operate at ambient temperature for 20 minutes.
(4)
Adjust the i 15-V power supplies to t 15 VDC
- 0.001 VDC.
(5)
Apply a 50% full scale input to the card using the system calibrator.
(6)i Record the outputs of each channel.
(7)
Adjust the +15-VDC power supply to +15.025 +. 0.001 VDC.
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(8)
Record the cutputs of each channel.
.(9)
Repeat steps (7) and (8) adjusting the + 15 VDC to + 1.5.050 VDC.
(10)
Repeat steps (7) and (8) using +14.975 VDC.
('1 ? ) Repeat steps (7) and (8) using +14.950 VDC.
~
(12)
Return the +15-VDC supply to 15 VDC t.001.
(13)
Repeat steps (7) to (11) adjusting the VDC supply to the negative values.
I 8.9 Arralog Isolator Interchannel Effects at Saturation (1)
Record the serial number of the card on the data sheet (Attach-1 ment 13).
i I
(2)
C'alibrate the card according to the appropriate functional test of Section 8.2.
(3)
Apply a 50% of full scale input to all the channels.
Record the outputs.
(4)
Continue to apply a 50% of full scale input to three channels and apply a 125% of full scale input to the fourth.
Record the outputs of all channels.
8.10 Analog Isolator Failure Mode Isolation (1)
Record the serial msnber of' the card on the data sheet (Attach-ment 14).
l' (2)
Connect a 4.7K 0 resistor.scross each of the outputs.
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'(3)
Calibrate the card according to the appropriate functional test of Section 8.2.
(4)
Connect a IK resistor and DMM across the input terminals. 215 volt power is applied for all tests.
(5)
Short across the 4.7K resistor.
(6)
Measure the DC voltage at the inputs and record on the data
. sheet.
(7); Remove the resistor, measure the DC voltage at the inputs and record on the data sheet.
(8). Connect 15 VDC across the output terminals with the polarity the same as the output. Measure the DC voltage on the inputs and
~
record on the data sheet.
(9)
Connect 15 VDC across the output terminals with the polarity opposite the output.
Measure the DC voltage on the. input and record on the data sheet.
' (10)
Connect 120 VAC through a 10K.0, 2-watt resistor to the ou.tput terminals.
Measure the AC voltage on the inputs and record on the data sheet.
l 8.11 Analog Isolator Bandwith (1)
Record the serial number of the card on the data sheet ( Attach-ment 15).
(2)
Calibrate the card according to the appropriate functional test of Section 8.2.
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(3)
Apply a square wave from the function generator with a sagnitude of 1005 of full scale input and a duration (T) calculated from the equation below to, the inputs of the card.
T = 10 RC where R and C are taken from EI DWG No. 00796.
Channel R
C 1
1 R4 + 1/2 R5 C1 2
Rg3 + 1/2 Rg4 C4 3
R22 + 1/2 R23 C7 4
R31 + 1/2 R32 10,
C (4)
Record the value of RC for the channel on the data sheet.
(5)
Connect the oscilloscope and the wavefom generator as shown on Figure 8.
- (6)
Mjust the oscilloscope to display the output of the isolator exactly between the 05 and 1005 graticle lines.
(7)
Mjust the sweep to disp 1'ay approximately 5 RC.
(8)
Enter on the data sheet the time taken for the output to rise from zero to the 635 line on the graticle.
(9)
Repeat steps (4) through (8) for all channels on the card.
9.0 POSTTEST
.(1)
Remove all test equipment and test leads and fixtures.
(2)
Return all isolator cards to controlled storage for proper storage.
g.j REvislON NO.
PROCEDURE NO. EIP-24 0
JOB CODE-S/N PAGE 22 OF 33 6
(3)
Submit all data sheets and data acceptance theets to the respon-sible engineer for review and teceptance or rsjection of the
- tested cards.
10.0 ACCEPTANCE CRITERIA 10.1 Digital Isolator Functional Test (1)
Output less than 1 volt for an input less than 6 volts (DC for -1 assembly, AC RMS for -2 assembly).
(2)
Output greater than or equal to 3.8 volts for input voltage
' reater t.'.an 45 volts.
g 10.2 Anal'og Isolator Functional Test (1).' Outputs within 0.15 of output span for inputs at high and low ifmits of input span.
10.3 HI-Potential Isolation Tests (DC and AC) i (1)
Leakage current less than 1 uADC at 3 KVDC.
(2)
Leakage current less than 200 uAAC ras at 1.5 KVAC.
10.4 Surge Withstand Capability Test (1)
The channel fails if "zero" and/or " gain" adjustments cannot be made to bring amplifier output to' within tolerances after SWC test.
(2)
The channel fails if after the SWC test the output fails to return to within 0.1% of the output span of the pre-SWC test value.
65 REvislON NO. _. PROCEDURE NO.
rip.na 0
J08 CODE-8/N PAGE 23 0F 33 Eo. bay 9
t
10.5 Thermal Drift (1) Output change of less than 0.015% of output span per *C for the range of 10*C to 40*C.
10.6 Linearity (1) Output variance from tracking' the input is less than 0.1% of the output span.
10.7 Power Supply Drift (1) Output change less than 0.1% of the output span.
10.8 Interchannel Effect at Saturation (1) Output change less than 0.05% of the output span.
10.9 Failure Mode Isolation (1) Voltage at the input of less than 0.01% of input span.
10.10 Bandwidth (1) Rise time measured (t) within 20% of calculated (RC).
11.0 RETEST (1) Any card failing the acceptance criteria shall be returned to the card vendor for repair.
(2) The repaired card shall be ratested according to the appropriate section of this procedure and the retest data recorded on the -
appropriate data sheet.
6.1 REVISION NO.
PROCEDURE NO.
EIP-24
. ~. - n s'l
- 12.0 FINAL REVIEW All applicable steps of this procedure have been perfonned as written and all signatures and other verifications are complete.
r(
h
]
Test Engineer SignaturekM
- hm Date ZTAu6 fH.
QC Representative Signa
/bs/~ ( 4 st a Date
/- 2 r M Qualification level of test engineer verified to level II or III per QAP 10-2.
g [
f((
Functionat Manager Signatu te t
7 Test procedure approved for use.
ProjectManagerSignatureb$wlelI>
DateShlMb O
i I
S f
7tl ngvis10N NO.
..P.R_OCEDURE NO.
rip-ra 0
Joe Coot-S/N PAGE 25 0F 33 Kev *o.1;a" c
PS 9
+ t 15v JI INPUT
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7 C 3 C
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( 93 El N ti 25 56 22 f
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AMP CONNECTOR PARTS NEEDED 288 2F, is 19 48
-s 14,)
I6 PLUG PART AMP No.
C 3
- q4f, 27s 87 38 28e(
PS Plug 206708-1 A
> 4 2,
'I-Cable Clamp 206966-1 (5) Socket 205090-1 or 66602-1 JO Plug 205839-3 Cable Clamp 206070-1
-(18) Socket 205090-1 or 66602-1 JI Plug 206437-1 Cable Clamp 206512-1 (32) Pin 205089-1 Test Connector :
EIP-24 Page 26 of 33
a INPUT S YSTEf4 CALIBR AT0R E
.l p.= =. e = -o 3
a u.,,,.
s'
~
9 to it it 13 OUTPUT 19 I
I 15 g
la i
3 87 4
'l g
19 4
20 T
2:
T 22 9
23 to 19 i
25 3
ts 13 O
G 27
'TT W
1s DMM 3
sy 33 1
OUTPUT TEST CONNECTIONS l
CHANNEL 000 CARD EVEN CARD
~~
1 2
17 2
4 15 i
t 3
6 13 i
4 8
11 5
1 18 6
3 16-7 5
24 8
7 12 Com 9
10 i
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j FIGURE 2 j
Digital Isolator Functional TesE. Configuration EIP-24 Dano 77 ef '11
._ _=
J INPUT HIPOT TESTER S C AT
- 3. o My 2
Ac p 1.5 m v
.J 4
LOW SHD N14H 5
O O
O T
ODD 7
cans 8
HIG H io I f 1
To ISOLATOR FRAME
'1 T
OUTPUT 19 ODD 15 l
CARD EVEN to 2
7 LOW CARD 17 o
nisu v
I le 6
7 2t T
Y 1
q 23 so 24 1I EVEN 25 l
CARD 26 1
LOW l
g 27 W
g5 tt
^
gs 30
,7 3
J.E 1
DC Test may be conducted on both cards simultaneously.
AC Test to be run on one card at a time.
~
~"
FIGURE 3 7lj Digital Isolator Isolation Test Configuration EIP-24~
Pace 28 of 33 t,-
-z-=
9 INPUT SYSTEM E
i
_L CALIBRATER J
E 1
1-6 a
i
)
io i
.JL is
_T OUTPUT 39 A.
2 i
~f-IT T
fL.
l
+
3 ti T
.n.-
T gg 24 u
l
-- f ee I1 i
19
~:_--.-
DMM 3.
i6 x
1
~' ~
TEST CONNECTIONS
- ~ -
CHANNEL 000 CARD EVEN CARD INPUT 0JTPUT INPUT OUTPUT
(+) (-)
(+)(-)
(+) (-)
(+)(-)
1 13 16 8
7 29 32 11 12 2
5 8
6 5
21 24 13 14 3
9 12 4
3 25 28 15 16 4
1 4
2 1
17 20 17 18
- gent;gpigtgmgaygconnectgd in serieg1g simultaneous adjustment e yo ge pu s connec n para FIGURE 4 Analog Isolator Functional Test'%onfiguration 71 I
EIP-24 pan. 9a nr is 0
INPUT HIPOT TESTER se av s.o uw
.3 ACAT 4.s nv LOW GND HIGH 1
OOO s
7 8
cAS weau 10 if 1
i it opp To 150LATom FR AME
'"ir' OUTPUT CARD 19 LOW I
11 i
se tvtN y
CARD 73-1 Hl6H 1
19 7
28 i
T Y
T Tr i
i cvEN le CARD 25 I
Low 16 l
gg 27
!1.
T is at is 30 87 L
Jf 7.*
I
- ~ DC Test may be conducted on both cards simu,1taneously.
AC Test to be run on one card at a time.
l
~~.
I FIGURE 5 i
t i) j Analog Isolator Isolation fest Configuration EIP-24 t
r IN PUT H,G H Q SWC TESTER t.o w C a*a sTNC 1
O O
s l
T 8
i 9
to JL i
is ir i
curPUT TE'
_L m Jr_
i V
i z
L 6
to l
T 15 i
Y 32 T
w 4
.e l
nn O
OsY"c X
en. :
g 3
i
_9_
ca
- SCOPE 2'
1 o
i is e,
i 3'
(Analog Channel Shown)
- 7 1
l
{
DIGITAL !$0LATOR
~ -
g l
CHANNEL 000 CARD EVEN CARD
(+)IN(-)
OUTPUT maammm(mm)mmm(mm)mm:
+ !N -
OUTPUT nummmmmmmmm l
1 1
9 2
17 25 17 i
2 2
10 4
18 26 15 1
2 3
11 6
Ig 27 13 l"ogIsslator 4
4 12 8
20 28 11 5
5 13 1
21 29 18 i sts and Outputs 6
6 14 3
22 30 16
! :ed on Figure 7.
7 7
15 5
23 31 14 i
8 8
16 7
24 32 L2 Com g
- ,o FIGURE E i
Surge Withstand capability Transverse Mode Test Configuration a
's
INPUT 1
HtG H C to n
o SWC TESTER
'awc moa svac
_J O
o Y
t
_1,.
to
_n_
,1 T
ouYPuT PS,
X 1
7 es 4
v y
ir t
_.s_
s 21 6
18 26 l
T Y
SS i
T v
77 sg n
O OsVNC
[
l X
cu.e M
g cy SCOPE y
es l'
is 38 (Analog Channel Shown) 1 l
,.!,g_
ANALOG ISOLATOR aH CHANNEL DDD CARD EVEN CARD
(+)!N(-)
(+)0UT(-)
-(+)!N(-J
(+)00T(-)
1 j
num -mmmmmmmmmm --
i 1
13 16 8
7 29 32 11 12 igital Isolato.r 2
5
'8 6
5 21 24 13 14
!1putsand 3
9 12 4
3 25 28 15 16 l
i Jtputs listed 4
1 4
2 1
17 20 17 18 i 1 Figure 6.
l
(
FIGURE 7 l
i i
Surge Withstand Capability Comenon, Mode Test Configuration f
~
E!P-24 l
Page 32 of 33
IN PUT S
._L.
WAVEFORM i
M 3
~
GENERATOR g
L.
_k.
7 9
to l.l s1 T
i OUTPUT E!
E A
O ss l
O 8"M v
SYNC gy T
._s_
SCOPE 1.
7 6
T i
l
'T' 8'
[
U
...z.................___
se ii I
Y
.J,1 os....!
I E
L.
........._....t 27 I
!1.
l I
"iT es I
is I
t 38 s
31 87 e
l l
=
g-os
,.....p.................g E.,
+49 I
g
,e 7,
e..-
Sets Figure 4 for Test Connections Table t
FIGURE 8'.
7S Analog Isolator Bandwidth Test Configuration
,.-e,-...
.~.
q.
4 -t-i -
EIP 37: Energy Incorporated Integrated Test-Procedure for Analog and Digital Isolation System, including Design Basis System Fault Testing i
1 L1/NRC/ae
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