ML20077F414
| ML20077F414 | |
| Person / Time | |
|---|---|
| Site: | Palo Verde  |
| Issue date: | 06/30/1983 |
| From: | ABB COMBUSTION ENGINEERING NUCLEAR FUEL (FORMERLY |
| To: | |
| Shared Package | |
| ML18023A035 | List: |
| References | |
| CEN-219(V)-NP-R01, CEN-219(V)-NP-R1, CEN-219-(V)-NP, NUDOCS 8308010374 | |
| Download: ML20077F414 (25) | |
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PALO VERDE NUCLEAR GENE.tATING STATION l UNIT 1 l CEN-219(V)-NP
- REVISION 01
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CPC/CEAC SYSTEM PHASE II SOFTWARE VERIFICATION TEST REPORT JUNE, 1983
, combustion Engineering, Inc.
I Nuclear Power Systems
. Power Systems Group Windsor, Connecticut 8308010374 830727 PDR ADOCK 05000528 E PDR 5
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l LEGAL NOTICE THIS REPORT WAS PREPARED AS AN ACCOUNT OF WORK SPONSORED BY COMBUSTION ENGINEERING, INC. NEITHER COMBUSTION ENGINEERING NOR ANY PERSON ACTING ON ITS BEHALF:
A. MAKES ANY WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED INCLUDING THE WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY, WITH RESPECT TO THE ACCURACY, COMPLETENESS, OR USEFULNESS OF THE INFORMATION CONTAINED IN THIS REPORT, OR THAT THE USE OF ANY INFORMATION, APPARATUS, METHOD, OR PROCESS DISCLOSED IN THIS REPORT MAY NOT INFRINGE PRIVATELY OWNED RIGHTS; OR i 8. ASSUMES ANY LIABILITIES WITH RESPECT TO THE USE OF, OR FOR
- DAMAGES RESULTING FROM THE USE OF, ANY INFORMATION, APPARATUS, METHOD OR PROCESS DISCLOSED IN THIS REPORT.
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ABSTRACT Phase II Testing is performed on the CPC/CEAC System to (1) verify that the CPC and CEAC software modifications have been properly integrated with the CPC and CEAC software and system hardware and (2) provide
, confirmation that the static and dynamic operation of the integrated system as modified is consistent with that predicted by design analyses,
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which provide design inputs to CPC/CEAC Functional Design Specifications.
l This report presents the Phase II test results for the Arizona Nuclear Power Project, PVNGS-1 Plant CPC/CEAC Rev. 00, software.
The Ph'ase II software verification tests have been performed as required in Reference 1. In all cases, the test results fell within the acceptance criteria, or are explained. The test results indicate that the CPC and CEAC software has no indication of software error and that the operation of the integrated system is consistent with the performance predicted by design analyses.
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TABLE OF CONTENTS Section Title Page No.
1.0 INTRODUCTION
5 1.1 Objectives 5 1.2 Description of Phase II Testing 6 1.3 Applicability 6 2.0 CPC/CEAC INPUT SWEEP TESTS 7 2.1 CPC Input Sweep Test Case Selection 7 2.1.1 CPC Processor Uncertainty Results 7 2.1.2 Analysis of CPC Input Sweep Test Results 8
- 2. 2 CEAC Input S'eep w Test Case Selection 10 2.2.1 CEAC Processor Uncertainty Results 10 2.2.2 Analysis of CEAC Input Sweep Test Results 10 l 3.0 DYNAMIC SOFTWARE VERIFICATION TEST 11 3.1 DSVT Case Selection 11 3.2 Generation of DSVT Acceptance Criteria 12 3.3 DSVT Results 18 3.4 Analysis of DSVT Results 20 4.0 LIVE INPUT SINGLE PARAMETER TEST '
, 21 4.1 LISP Test Case Selection 21 4.2 Generation of LISP Acceptance Criteria 22 4.3 LISP Test Results 23 5.0 PHASE II TEST RESULTS
SUMMARY
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6.0 REFERENCES
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1.0 INTRODUCTION
I The verification of software modifications of the CPC/CEAC System )
consists of several steps which address two major areas of the l modification process: l (1) Specification of sof,tware modifications (2) Implementation of software modifications The specification of software modifications is documented in the CPC and CEAC Functional Design Description and the Data Base Listing and is verified by design analyses contained in recorded 4
calculations. The implementation of software modifications is documented in Software Design Specifications and assembly listings.
The verification process for the modified software implementation includes Phase I and Phase II software verification tests. l The requirements of the Phase II software verification testing are based on the fact that the Phase I testing has been previously performed. Successful completion of Phase I testing verifies the correct implementation of the modified software. Phase II testing completes the software modification process by verifying that the integrated CPC System responds as expected.
This document contains the test results and conclusions'for the Ph'ase II software verification test.
1.1 Objectives The primary objective of Phase II testing is to verify that the CPC and CEAC software modifications have been properly integrated with the CPC and CEAC software and system hardware. In addition Phase II testing provides confirmation that the static and dynamic operation of the integrated system as modified is consistent with that predicted by design analyses. These objectives are achieved 5
by comparing the response of the integrated system to the response predicted by the CPC/CEAC FORTRAN simulation code. This comparison is performed for a selected range of simulated static and dynamic input conditions.
1.2 Description of Phase II Testing Phase II testing consists of the following tests: \
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(1) Input Sweep Test, (2) Dynamic Software Verification Test, and (3) Live Input Single Parameter Test.
These tests are performed on a single channel CPC/CEAC System with integrated software that has undergone successful Phase I testing (Reference 2).
1.3 Applicability This report applies to the Phase II testing performed on the Arizona Nuclear Power Project, PVNGS-1 CPC/CEAC system software.
The software revisions documented in this report are designated as Revision Number 00 to the PVNGS-1 CPC/CEAC system software.
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2.0 CPC/CEAC INPUT SWEEP TESTS The Input Sweep Test is a real time exercise of the CEAC and CPC application software and executive software with steady-state CPC and CEAC input values read from a storage device. This test has the following objectives:
(1) To determine the processing uncertainties that are inherent in the CPC and CEAC designs.
(2) To verify the ability of the CPC and CEAC algorithms used in
'the system hardware to initialize to a steady state after an auto-restart for each of a large number of input combinations within the CPC/CEAC operating space, and (3) To complement Phase I. module testing by identifying any abnormalities in the CPC and CEAC algorithms used in the system hardware which were not previously uncovered.
2.1 CPC Input Sweep Test Case Selection
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)testcases,eachinvolvingdifferentcombinationsof process inputs and addressable constants, were used for CPC design
. qualification testing of the Revision 00 software.
2.1.1 CPC Processor Uncertainty Results For each test case, differencec in the results of the FORTRAN-simulation code and CPC system were calculated. A statistical analysis of these differences produced the processing uncertainties.
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The DNBR statistics did not include those cases for which the DNBR as calculated on either system was at the limits .
i This is because a difference of zero (or close to zero) would be computed and would incorrectly weight the distribution of differ-ences. A total of cases remained after these cases were-eliminated. TheLPistatisticsdidnotincludethosecasesfor
, which the LPD as calculated on either system was equal to or greater than the upper limit of -
core average kw/ft (=
kw/ft). A total of cases remained after these cases were eliminated.
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Although cases were not included in the computation of DN8R and LPD statistics, respectively, they were still included as Input Sweep test cases for the purpose of identifying potential software errors.
The processor uncertainties for DNBR and LPD are defined as the one-sided tolerance limits which encompass 95% of the distribution of DN8R and LPD differences for all test cases with a 95% confidence level. The processor uncertainties, determined from Input Sweep _
for DNBR and LPD_respectively are _ _ . ,
DNBR units, and -
core average kw/ft. However, since the distribution of differences is so restrictive the maximum error may be used (that is, the limits which encompass 100% of the difference). This is more conservative and'yet still results in small processor uncertainties. Thus defined, the processor uncertainties fo1 evision R 00 on DNBR and LPD are _
DN8R units and Tore average kw/ft, respectively. -
2.1.2 Analysis of CPC Input Sweep Test Results Theresultsofthetestcasesexceedingthe95/95h.olerancelimit were analyzed for evidences of software errors.
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The review results of the DNBR and LPD test cases outside the 95/95 tolerance limit will now be discussed. For DNBR there were
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cases below the lower tolerance limit of (DNBR
. units)_and test cases above the upper tolerance limit of (DN8R units). For these test cases the difference
'betwee the single channel and the"CPC Fortran is within the accuracy of the two systems. The largest percent error among the cases was .
These differences do not show a significant commonality since the differences are absolute (not relative) and it should be expected that the largest differences should occur at high DNBR's. It is therefore concluded that no errors are indicated in the CPC Single Channel DNBR program.
For LPD the cases examined were: ~]caseswithdifferencesbelow thelower95/95tolerancelimitof(,
, ](%ofcoreaverage kw/ft), cases with differences greater than the upper tolerance I "~
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limit of .
The largest percent error among the cases was 2 . The
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commoninputtothesetestcaseswasfoundinotNertes'tcases with less maximum difference and less percent error. Examination of the inputs to all -
LPD cases outside the tolerance limits showed that the inputs covered a wide spectrum. No common area was found. It is therefore concluded that there is no indication from the Input Sweep test results of software errors in the Single Channel calculation of LPD.
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- 2. 2 CEAC Input Sweep Test Case Selection test cases, each involving different combinations i of CEAC process inputs were used for CEAC design qualification testing of the Revision 00 software. These test cases covered all CEAC operating space.
2.2.1 CEAC Processor Uncertainty Results For each test case, differences between the CEAC FORTRAN simulation code and CEAC single channel system results were calculated. The processor uncertainties for DNBR and LPD are defined as the one-sided tolerance limits which encompass 95% of the distribution of DNBR and LPD penalty factor differences for all test cases with a 95% confidence level.
The processor uncertainties for the DNBR and the_LPD penalty factor differences are respectively.
2.2.2 Analysis of CEAC Input Sweep Test Results The results were reviewed for representativeness and for any evidence of computational differences between the CPC FORTRAN simulation and the Single Channel Facility (SCF). The test data produced penalty factors which swept the respective DNBR.and LPD penalty factor ranges with emphasis on the midrange values. The differences between the penalty factors from the SCF and the FORTRAN simulation were within a range which is justified by the differences in word length. There was one casa in which the packed penalty factor words from the Single Channel Test Facility (SCTF) and from the Fortran simulation differed. This difference was in the last significant bit of the DNBR penalty factor and was found to be due to the limited precision of the conversion constants. Therefore, it was concluded that the results of the test cases did not indicate the existence of software errcrs.
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i 3.0 DYNAMIC SOFTWARE VERIFICATION TEST The Dynamic Software Verification Test (DSVT) is a real time exercise of the CPC application software and executive software with transient CPC input values read from a storage device. This test has two objectives:
(1) To verify that the dynamic response of the integrated CPC software is consistent with that predicted by design analyses, and (2) To supplement design documentation quality. assurance, Phase I module tests, and Input Sweep Tests in assuring correct implementation of software modifications.
Further information concerning DSVT may be found in Reference 1.
3.1 DSVT Case Selection Test cases for DSVT are selected to exercise dynamic portions of the CPC software with emphasis on those portions of the software that have been modified.
, DSVT requires that, as a minimum, cases be selected for testing (Reference 1). These cases are from the Phase II test series (identified in Reference 1) and consist of a
, The entire series of DSVT test cases was executed, using the g CPC/CEAC FORTRAN simulation code and the single channel facility with the Rev. 00 CPC software. Because PVNGS-1 has one fewer regulating CEA banks than previous CPC protected plants, only of the usual subcases needed to be executed
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shutdown sequence represented by case . Subcase 7 ***
. J retained in a dummy format to preserve a test case numbering l
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l sequence which_was consister.t with ~~previous tests. In addition, i
cases , each consisting of subcases, were executed to test the CPC/CEAC response to reactor power cutback.
l 3.2 Generation of DSVT Acceptance Criteria
, , Acceptance criteria for DSVT are defined (in Reference 1) as the trip times and initial values of DNBR and LPD for each test case.
These trip times and initial values are generated using the certified CPC/CEAC FORTRAN simulation code. Processing uncer-tainties obtained during Input Sweep testing are factored into the acceptance criteria for initial values of DNBR and LPD where necessary. Trip times are affected by program execution lengths as well as by the Input Sweep uncertainties. The minimum, average, and maximum execution lengths (in milliseconds) calculated for the Revision 00 software are listed below.
CPC Application Program Execution Lengths Program Minimum Average Maximum (msec) (msec) (msec)
FLDW UPDATE POWER ,
STATIC Each DSVT case was initially executed once with norainal program execution lengths (values between the minimum and maximum) and
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data base values of trip setpoints using the CPC/CEAC FORTRAN simulation code. Following execution of the same cases using the single channel facility, the single case which did not yield h DNBR trip time equivalent to that calculated by the CPC FORTRAN code was re-analyzed.
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I This DSVT case was re-executed once with nominal execution lengths and the most conservative DNBR trip setpoint and once with nominal execution lengths and the least conservative DNBR trip setpoint.
This process produced a bandwidth of trip times for the test case which contained the effects of processing uncertainties.
The software DSVT program includes a( millisecond interrupt cycle in order to check for DNBR and LPD trip signals. This
. results in a ]millisecondintervallimitontriptimeresolution which is factored into the acceptance criteria. The following tables contain the final DSVT acceptance criteria for initial values and trip times for DN8R and LPD.
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I Acceptance Criteria for DN8R and LPD Initial Values (DNBR Units and kw/ft., respectively)
DNBR DNBR LPD LPD Test Case (Mi n._ ) (Max.) (Min.) (Max.)
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Acceptance Criteria for DNBR and LPD Initial Values (DNBR Units and kw/ft., respectively)
(Cont.)
ONBR DNBR LPD LPD Test Case (Min.) (Max.) (Min.) (Max.)
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Acceptance Criteria for DNBR and LPD Trip Times (seconds)
DNBR Trip DN8R Trip LPD Trip LPD Trip Test Case (Min.) (Max.) (Min.) (Max.)
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Acceptance Criteria for DNBR and LPD Trip Timas (seconds)
DNBR Trip DNBR Trip LPD Trip LPD Trip Test Case (Min.) (Max.) (Min.) (Max.)
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w DSVT TEST RESULTS Initial Initial DNBR LPD DNBR Trip LPD Trip Test Case (DNBR Units) (kw/ft.) (sec.) (sec.)
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DSVT TEST RESULTS Initial Initial DNBR LPD DNBR Trip LPD Trip Test Case (DN8R Units) (kw/ft.) (sec.) (sec.)
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3.4 Analysis of DSVT Results
, The trip times for all of the test cases executed on the single channel facility met the acceptance criteria determined by the CPC/CEAC FORTRAN simulation code.
, For all test cases with the exception of , the initial values of DNBR and LPD were within the band widths definec by the FORTRAN simulation code which include the processing uncertainties obtained from the CPC Input Sweep Tost. For cases the initial values of LPD were outside the upper limits determined by applying the uncertainties derived from input sweep testing to_ ,
the FORTRAN results. -
The differences were kw/ft for cases J, respectively, corresponding to I qp _ - -
_j er cent core avg. kw/ft. These errors are less than the magnitude of the_ largest lower limit difference determined from input sweep testing - aper cent core avg. kw/ft) and can be attributed to roundoff errors in A/D conversion and % core avg. kw/ft to kw/ft conversion.[ No software error is indicated.
Test cases . _ are cases with the inputs initially defining a trip condition. In the CPC FORTRAN simulation code, one program execution cycle is needed to generate r trip output.
This implies an acceptance criterion of sec. for minimum and maximum time-to-trip, while the actual
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Erip times for the CPC single channel were lsec. These FORTRAN cases,were examined to verify that a trip condition existed at ,
time .
, justifying the indicated acceptance criteria for time-to-
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trip of;6 sec., consistent with the expected CPC single channel response.
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4.0 LIVE INPUT SINGLE PARAMETER TEST The Live Input Single Parameter test is a real-time exercise of the CPC/CEAC application and executive software, "?S transient CPC/CEAC input values generated from an external source and read through the CPC/CEAC input hardware. The objectives of this test are:
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(1) To verify that the dynamic response of the integrated CPC/CEAC software and hardware is consistent with that predicted by design analyses.
(2) To supplement design documentation quality assurance, Phase I module tests, Input Sweep Tests, and DSVT in assuring correct implementation of software modifications.
(3) To evaluate the integrated hardware / software system during operational modes approximating plant conditions.
l 4.1 LISP Test Case Selection Reference 1 identifies the test cases to be used for LISP. These cases are the single variable dynamic transient test cases from the Phase II test series. In addition, a test case is included to test the Reactor Power Cutback (RPC) feature. '.
These test cases, which are applicable to PVNGS-1, consist of a 4
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4.2 Generation of LISP Acceptance Criteria The acceptance criteria for LISP are based on trip times for the dynamic test cases. For the RPC test case, there should be no trip during RPC.
l , These cases are simulated in the CPC FORTRAN simulation code and l contain the following adjustment components.
O Application program execution lengths used for LISP testing were the same as those for DSVT, with the addition of CEAC minimum and maximum execution lengths of , asec, respectively.
The final acceptance criteria (generated by the CPC FORTRAN simulation code and adjusted for the above components) for LISP also include
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an7 are contained in the following table.
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Test Case Minimum Trip Time Maximum Trip Time (seconds) (seconds)
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4.3 LISP Test Results j The dynamic transients were executed on the CPC Single Channel
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facility. The recorded trip times (in seconds) for each case are listed in the following table:
, , Run #17 #18 #19 #20 #21 #28-A All recorded trip times met the final acceptance criteria for LISP. The result of test case showed that the RPC feature, as expected, caused no CPC trip"when the single bank RPC was inserted.
Major aspects of the system diagnostic features were verified.
These include the trips buffer and failed sensor reports, CPC and CEAC Point ID's, and correct operation of CEAC displays and operator's module lamp indications. All aspects of automated
, reentry of Addressable Constants were also tested. Prior to the final verification, a change to the system monitor task was made to correct an inconsistency observed in the' printout of a datum being stored on the addressable constants disk. A byte by byte comparison was made between the new disk and the backup of the
- previous (anrevised) disk and it was shown that only this portion of the p'ogram was affected. Thus all previous testing were determined to be acceptable and the system diagnostic features were correctly implemented.
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5.0 PHASE II TEST RESULTS
SUMMARY
The Phase II software verification tests have been performed as required in Reference 1. The test results indicate that the CPC and CEAC software has no indication of software errors and that the operation of the integrated system is consistent with the a performance predicted by design analyses, which provide design inputs to CPC/CEAC Functional Design Specifications.
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6.0 REFERENCES
- 1. CPC Protection Algorithe Software Change Procedure CEN-39(A)-P, Revision 02, December 21, 1978.
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- 2. Paio Verde Nuclear Generating Station Unit 1, Cycle 1 CPC/CEAC
, System Phase I Test Report, CEN-217(V)-P, Revision 01, June 1983.
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