ML20071E708
| ML20071E708 | |
| Person / Time | |
|---|---|
| Site: | Palo Verde  |
| Issue date: | 01/31/1983 |
| From: | ABB COMBUSTION ENGINEERING NUCLEAR FUEL (FORMERLY |
| To: | |
| Shared Package | |
| ML17298A229 | List: |
| References | |
| CEN-219(V)-NP, CEN-219(V)-NP-R, CEN-219(V)-NP-R00, NUDOCS 8303100353 | |
| Download: ML20071E708 (28) | |
Text
PALO. VERDE NUCLEAR GENERATING STATION UNIT 1
%Y -
CEN-219(V)-NP
,A-REVISION 00
~
n CPC/CEAC SYSTEM PHASE II SOFTWARE VERIFICATION TEST REPORT JANUARY, 1983 Combustion Engineering, Inc.
Nuclear Power Systems Power Systems Group Windsor, Connecticut i
8303100353 830303 PDR ADOCK 05000528 E
1 t
3 LEGAL NOTICE THIS REPORT WAS PREPARED AS AN ACCOUNT OF WORK SPONSORED BY COM8USTION ENGINEERING, INC. NEITHER COMBUSTION ENGINEERING NOR ANY PERSON ACTING ON ITS BEHALF:
A.
MAKES ANY WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED INCLUDING THE WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY, WITH RESPECT TO THE ACCURACY, COMPLETENESS, OR USEFULNESS OF THE INFORMATION CONTAINED IN THIS REPORT, OR THAT THE USE OF ANY INFORMATION, APPARATUS, METHOD, OR PROCESS DISCLOSED IN THIS REPORT MAY NOT INFRINGE PRIVATELY OWNED RIGHTS; OR B.
ASSUMES ANY LIABILITIES WITH RESPECT TO THE USE OF, OR FOR DAMAGES RESULTING FROM THE USE OF, ANY INFORMATION, APPARATUS, METHOD OR PROCESS DISCLOSED IN THIS REPORT.
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ABSTRACT Phase II Testing is performed on the CPC/CEAC System to (1) verify 1
that the CPC and CEAC software modifications have been properly integrated with the CPC and CEAC software and system hardware and (2) provide confirmation that the static and dynamic operation of the integrated 6
system as modified is consistent with that predicted by design analyses.
This report presents the Phase II test results for the Arizona Nuclear Power Project, PVNGS-1 Plant CPC/CEAC Rev. 00, software.
The Phase II software verification tests have been performed as required in Reference 1.
In all cases, the test results fell within the acceptance criteria or the results were analyzed to ider,tify the reason for the discrepancy.
Those open items discussed in Sections 3.4 and 4.3 will be resolved before the Software Package is transmitted to the Arizona Nuclear Power Project, and a supplement will be submitted to this Phase II Test Report.
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l' TABLE OF CONTENTS l
Section Title Page No.
1.0 INTRODUCTION
5 1.1 Objectives 5
1.2 Description of Phase II Testing 6
1.3 Applicability 6
2.0 CPC/CEAC INPUT SWEEP TESTS 7
2.1 CPC Input Sweep Test Case Selection 7
2.1.1 CPC Processor Uncertainty Results 7
2.1.2 Analysis of CPC Input Sweep Test Results 8
2.2 CEAC Input Sweep Test Case Selection 10 2.2.1 CEAC Processor Uncertainty Results 10 2.2.2 Analysis of CEAC Input Sweep Test Results 10 3.0 DYNAMIC SOFTWARE VERIFICATION TEST 11 3.1 DSVT Case Selection 11 3.2 Generation of DSVT Acceptance Criteria 12 3.3 DSVT Results 18 3.4 Analysis of DSVT Results 20 4.0 LIVE INPUT SINGLE PARAMETER TEST 22 4.1 LISP Test Case Selection 22 4.2 Generation of LISP Acceptance Criteria 23 4.3 LISP Test Results 24 l
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5.0 PHASE II TEST RESULTS
SUMMARY
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6.0 REFERENCES
27 4
1.0 INTRODUCTION
The verification of software modifications of the CPC/CEAC System consists of several steps which address two major areas of the modification process:
0 (1) Specification of software modifications (2)
Implementation of software modifications The specification of software modifications is documented in the CPC and CEAC Functional Design Description and the Data Base Document and is verified by design analyses contained in recorded calculations.
The implementation of software modifications is documented in Software Design Specifications and assembly listings.
The verification process for the modified software implementation includes Phase I and Phase II software verification t'ests.
The requirements of the Phase II software verification testing are based on the fact that the Phase I testing har been previously performed.
Successful completion of Phase I testing verifies the correct implementation of the modified software.
Phase II testing completes the software modification process by verifying that the integrated CPC System responds as expected.
This document contains the test results and conclusions for the Phase II software verification test.
o 1.1 Objectives The primary objective of Phase II testing is to verify that the CPC and CEAC software modifications have been properly integrated with the CPC and CEAC software and system hardware.
In addition Phase II testing provides c nfirmation that the static and dynamic operation of the integrated system as modified is consistent with that predicted by design analyses.
These objectives are achieved 5
4 by comparing the response of the integrated system to the response predicted by the CPC/CEAC FORTRAN simulation code.
This comparison is performed for a selected range of simulated static and dynamic input conditions.
1.2 Description of Phase II Testing Phase II testing consists of the following tests:
(1)
Input Sweep Test, (2) Dynamic Software Verification Test, and (3) Live Input Single Parameter Test.
Thes'e tests are performed on a single channel CPC/CEAC System with integrated software that has undergone successful Phase I testing.
1.3 Applicability This report applies to the Phase II testing performed on the Arizona Nuclear Power Project, PVNGS-1 CPC/CEAC system software.
The software revisions documented in this report are designated as Revision Number 00 to the PVNGS-1 CPC/CEAC system software.
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2.0 CPC/CEAC INPUT SWEEP TESTS The Input Sweep Test is a real time exercise of the CEAC and CPC application software and executive software with steady-state CPC and CEAC input values read from a storage device.
This test has the following objectives:
(1) To determine the processing uncertainties that are' inherent in the CPC and CEAC designs.
(2) To verify the ability of the CPC and CEAC algorithms used in the system hardware to initialize to a steady state after an auto-restart for each of a large number of input combinations within the CPC/CEAC operating space, and (3) To complement Phase I module testing by identifying any aonormalities in the CPC and CEAC algorithms used in the system hardware which were not previously uncovered.
2.1 CPC Input Sweep Test Case Selection
]testcases,eachinvolvingdifferentcombinationsof process inputs and addressable constants, were used for CPC design qualification testing of the Revision 00 sof tware.
2.1.1 CPC Processor Uncertainty Results For each test case, differences in the results of the FORTRAN simulation code and CPC system were calculated.
A statistical analysis of these differences produced the processing uncertainties.
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The DN8R statistics did not include those cases for which the DNBRascalculatedoneithersystemwasatthelimits[
).
This is because a difference of zero (or close to zero) would be computed and would incorrectly weight the distribution of differ-Atotalof[
]casesremainedafterthesecaseswere ences.
eliminated.
The LPD statistics did not include those cases for which the L9D as calculated on either system was equal to or greaterthantheupperlimitof[
] core average kw/ft (=[
]
kw/ft). Atotalof[
]casesremainedafterthesecaseswere eliminated.
Although(
)caseswerenotincludedinthecomputation of DNBR 'and LPD statistics, respectively, they were still included as Input Sweep test cases for the purpose of identifying potential software errors.
The processor uncertainties for DNBR and LPD are defined as the one-sided tolerance limits which encompass 95% of the distribution of DNBR and LPD differences for all test cases with a 95% confidence level.
The processor uncertaintie,s determined from Input Sweep,
for DNBR and LPD respectively are DNBRunits,and(
]coreaveragekw/ft.
- However, since the distribution of differences is so restrictive the maximum error may be used (that is, the limits which encompass 100% of the difference).
This is more conservative and yet still results in small processor uncertainties.
Thus defined, the
,rocessoruncertaintiesgrRevision00onDNBRandLPDare p
g DNBRunitsand[
]
core average kw/ft, respectively.
2.1.2 Analysis of CPC Input Sweep Test Results The results of the test cases exceeding the 95/95 tolerance limit were analyzed for evidences of software errors.
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i The review resulns of the DNBR and LPD test cases outside the 95/95 tolerance limit will now be discussed., For DNBR t,here were
[]casesbelow-thelowertolerancelimitof
,(DNBR
, units)and[]testcasesabovetheuppertolerancelimitof(
)
(DNBR units).
For these[ ] test cases the difference between the single channel and the CPC Fortran is within the accuracy of the two systems.
i These differences do not show a significant commonality since the differences are absolute (not relative) and it should be expected that the largest differences should occur at high DNBR's.
It is s
therefore concluded that no errors are indicated in the CPC Single Channel DNBR program.
For LPD the cases examined were: [ ] cases with differences below thelower95/95tolerancelimitof(
](%ofcoreaverage kw/ft),[ ] cases with differences greater than the upper tolerance limitof[
).
Thelargestpercenterroramongthe[]caseswas(
).
The I
common input to these test cases was found in other test cases with less maximum difference and less percent error.
Examination oftheinputstoall[]LPDcasesoutsidethetolerancelimits showed that the inputs covered a wide spectrum.
No common area was found.
It is therefore concluded that there is no indication i
from the Input Sweep test results of software errors in the Single Channel calculation of LPD.
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2.2 CEAC Input Sweep Test Case Selection i
[
)testcases,eachinvolvingdifferentcombinations of CEAC process inputs were used for CEAC design qualification testing of the Revision 00 software.
These test cases covered all CEAC operating space.
z.2.1 CEAC Processor Uncertainty Results For each test case, differences between the CEAC FORTRAN simulation code and CEAC single channel system results were calculated.
The processor uncertainties for DNBR and LPD are defined as the one-sided tolerance limits which encompass 95% of the distribution of DNBR and LPD penalty factor differences for all test cases with a 95% confidence level.
The processor uncertainties for the DNBR and the,LPD penalty factor differences are respectively.
2.2.2 Analysis of CEAC Input Sweep Test Results The results were reviewed for representativeness and for any evidence of computational differences between the CPC FORTRAN simulation and the Single Channel Facility (SCF).
The test data produced penalty factors which swept the respective DNBR and LPD penalty factor ranges with emphasis on the midrange values.
The differences between the penalty factors from the SCF and the FORTRAN simulation were within a range which is justified by the differences in word length.
Therefore, it wasconcludedthattheresultsofthe[
] test cases did not indicate the existence of software errors.
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3.0 DYNAMIC SOFTWARE VERIFICATION TEST The Dynamic Software Verification Test (DSVT) is a real time exercise of the CPC application software and executive software with transient CPC input values read from a storage device.
This test has two objectives:
(1) To verify that the dynamic response of the integrated CPC software is consistent with that predicted by design analyses, and (2) To supplement design documentation quality assurance, Phase I module tests, and Input Sweep Tests in assuring correct implementation of software modifications.
Further information concerning DSVT may be found in Reference 1.
3.1 DSVT Case Selection Test cases for DSVT are selected to exercise dynamic portions of the CPC software with emphasis on those portions of the software that have been modified.
DSVTrequiresthat,asaminimum, cases (
} be selected for testing (Reference 1).
These cases are from the Phase II test series (identified in Reference 1) and consist of a All of the DSVT test cases were executed using the CPC/CEAC FORTRAN 11
simulation code and the single channel facility with the Rev. 00 CPC software.
Because PVNGS-1 has one fewer regulating CEA banks F
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f than previous CPC protected plants, only Joftheusual subcases needed to be executed in the shutdown sequence represented by case;;.
Subcase was retained in a dummy format to preserve a test case numbering sequence which was consistent with previous tests.
In addition, cases
, each consisting of
]subcases were executed to test the CPC/CEAC response to reactor power cutback.
3.2 Generation of DSVT Acceptance Criteria Acceptance criteria for DSVT are defined (in Reference 1) as the trip times and initial values of DNBR and LPD for each test case.
These trip times and initial values are generated using the certified CPC/CEAC FORTRAN simulation code.
Processing uncer-tainties obtained during Input Sweep testing are factored into the acceptance criteria for initial values of DNBR and LPD where necessary.
Trip times are affected by program execution lengths as well as by the Input Sweep uncertainties.
The minimum, average, and maximum execution lengths (in milliseconds) calculated for the Revision 00 software are listed below.
CPC Application Program Execution Lengths Program Minimum Average Maximum (msec)
(msec)
(msec)
F--
FLOW UPDATE POWER STATIC Each DSVT case was initially executed once with nominal program execution lengths and data base values of trip setpoints using the CPC/CEAC FORTRAN simulation code.
Following execution 12
of the same cases using the single channel facility, cases which did not yield trip times equivalent to those calculated by the CPC FORTRAN code were re-analyzed.
Each of these DSVT cases were re-executed once with the minimum execution lengths and most conservative DNBR and LPD trip setpoints and once with the maximum execution lengths and least conservative DNBR and LPD trip setpoints.
This process produced a bandwidth of trip times for each test case which contained the effects of processing uncertainties and variations in application program execution lengths.
ThesoftwareDSVTprogramalsoincludesa[]millisecondinterrupt cycle in order to check for DNBR and LPD trip signals.
This results in a( ] millisecond interval limit on trip time resolution which is factored into the acceptance criteria.
The following tables contain the final DSVT acceptance criteria for initial values and trip times for DNBR and LPD.
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i Acceptance Criteria for DNBR and LPD Initial Values (DNBR Units and kw/ft., respectively)
DNBR DNBR LPD LPD Test Case (Min.)
(Max.)
(Min.)
(Max.)
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Acceptance Criteria for DN8R and LPD Initial Values (DN8R Units and kw/ft., respectively)
(Cont.)
1 DN8R DN8R LPD LPD Test Case (Min.)
(Max.)
(Min.)
(Max.)
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Acceptance Criteria for.
DNBR and LPD Trip Times (seconds)
Tr P DN R Tr p LDT p Test Case Min.
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Acceptance Criteria for DNBR and LPD Trip Times (seconds)
DNBR Trip DNBR Trip LPD Trip LPD Trip Test Case (Min.)
(Max.)
(Min.)
(Max.)
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DSVT TEST RESULTS Initial-Initial DNBR LPD DNBR Trip LPD Trip Test Case (DNBR Units)
(kw/ft.)
(sec.)
(sec.)
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DSVT TEST RESULTS Initial-Initial DNBR LPD DN8R Trip LPD Trip Test Case (DNBR Units)
(kw/ft.)
(sec.)
(sec.)
W t
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3.4 Analysis of 05VT Results For all test cases, the initial values of DN8R and LPD were within
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those defined by the CPC/CEAC FORTRAN simulation code generated band widths which include the processing uncertainties obtained from the CPC Input 5 weep Test.
Test cases [
] are
~
cases with the plant initially in a trip condition.
In the CPC FORTRAN simulation code, one program execution cycle is needed to generate a trip output.
This implies an acceptance criterion of
[
]sec. for minimum and maximum time-to-trip, while the actual trip times for the CPC single channel were[ ] sec.
These FORTRAN cases were examined to verify that a trip condition existed at time [
] justifying the indicated acceptance criteria for time-to-tripof[-]sec.consistentwiththeexpectedCPCsinglechannel response.
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Modification of the data base requires a software change and sub-sequent repetition of affected portions of Phase I and II testing.
I The results of that testing will be issued as a supplement to this document.
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l 4.0 LIVE INPUT SINGLE PARAMETER TEST The Live Input Single Parameter test is a real-time exercise of the CPC/CEAC application and executive software, with transient CPC/CEAC input values generated from an external source and read through the CPC/CEAC input hardware.
The objectives of this test are:
(1) To verify that the dynamic response of the integrated CPC/CEAC software and hardware is consistent with that predicted by design analyses.
(2) To supplement design documentation quality assurance, Phase I module tests, Input Sweep Tests, and DSVT in assuring correct implementation of software modifications.
(3) To evaluate the integrated hardware / software system during operational modes approximating plant conditions.
4.1 LISP Test Case Selection Reference 1 identifies the test cases to be used for LISP.
These cases are the single variable dynamic transient test cases from the Phase II test series.
In addition, a test case is included to test the Reactor Power Cutback (RPC) feature.
These test cases, which are applicable to PVNGS-1, consist of a _.
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)
4.2 Generation of LISP Acceptance Criteria The acceptance criteria for LISP are based on trip times for the dynamic test cases..For the RPC test case, there should be no trip during RPC.
These cases are simulated in the CPC FORTRAN simulation code and contain the following adjustment components.
Application program execution lengths used for LISP testing were the same as those for DSVT, with the addition of CEAC minim.um and maximumexecutionlengthsof(
) msec,respectively.
The final acceptance criteria (generated by the CPC FORTRAN simulation code and adjusted for the above components) for LISP are contained in the following table.
Test Case Minimum Trip Time Maximum Trip Time
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(seconds)
(seconds) 23 9
4.3 LISP Test Results F
- Thel,
, dynamic transients were executed on the CPC Single Channel facility.
The recorded trip times (in seconds) for each case are listed in the following table:
O Run All recorded trip times met the final acceptance criteria for LISP.
Theresultoftestcase[
}showedthattheRPCfeature,asex-pected, caused no CPC trip when the single bank RPC was inserted.
Major aspects of the operator's module operation, particularly the Point ID verification and addressable constant range limits were tested.
As part of the testing, the CPC and CEAC Point ID tables were checked to assure that the Point ids displayed on the operator's module are the same as those listed in the Point ID tables.
)
_ThereweresomediscrepanciesinCPCPointIDs([
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9 will be resolved in the supplement to this document.
All aspects of automated reentry of Addressable Constants were tested and were determined to have been. correctly implemented.
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5.0 PHASE II TEST RESULTS
SUMMARY
The Phase II software verification tests have been performed as required in Reference 1.
In all cases, the test results fell within the acceptance criteria or the results were analyzed to identify the reason for the discrepancy.
Those open items discussed in Sections 3.4 and 4.3 will be resolved before the Software Package is transmitted to the Arizona Nuclear Power a
Project and a supplement will be submitted to this Phase II Test Report.
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6.0 REFERENCES
1.
CPC Protection Algorithm Software Change Procedure CEN-39(A)-P, Revision 02, December 21, 1978.
2.
Palo Verde Nuclear Generating St.ation Unit 1, Cycle 1 CPC/CEAC System Phase I Test Report, CEN-217(V)-P, Revision 00, January,1983.
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