ML20137L073
| ML20137L073 | |
| Person / Time | |
|---|---|
| Site: | Fort Saint Vrain  |
| Issue date: | 08/31/1984 |
| From: | ENERGY, INC. |
| To: | |
| Shared Package | |
| ML20137L062 | List: |
| References | |
| EIP-24, TAC-51242, NUDOCS 8509120329 | |
| Download: ML20137L073 (62) | |
Text
{{#Wiki_filter:: e a w- s - .e. - -14 , 0? W A0 < ENERGY INCORPORATED PROCEDURE DESCRIPTION TEST PROCEDURE FOR PERFORMANCE AND ISOLATION TESTING OF 1E ANALOG AND DIGITAL ISOLATORS DATE PREPARED 8Y / 8'30-8N CONTRACT NO. REVIEWED BY hu 84 RELEASE DATE 8/31/84 QUALITY ASSURANCE >O 1 A' "'3/~81 PREPARED FOR PROJECT MANAGER S' - - - - M##I ~T ua gr.,re,.A : A-d REVISIONS NOTE: All revisions are flagged with the symbol in the right margin where N is the number of the revision. Rev. 0 - Issued for Use - 8/31/84 FOR LHFORMATiCS! ni.gy ISSUE DATE AUG SfsBS
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8509120329 850826 hDR ADOCM 05000267 PDR <
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REVISION NO. PROCEDURE NO. EIP-24 0 1 3 JOB CODE- S/N PAGE OF FORM E-035 REV.1,ll/82
A s TABLE OF CONTENTS PAGE 1.0 PURP0SE............................................................ 6 2.0 RESP 0 NS I B I L IT I E S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Te s t E n g i n e e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Qual i ty Control Representative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.0 REFERENCE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Requi red Doc ume nts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 O th e r Re fe re nc e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Test Procedure Use........................................... 8 3.4 P roc e du re Do cume n ta ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.0 TEST EQUIPMENT REQUIRED............................................ 9 5.0 TE ST S I GN AL C HAR ACTE R I ST I C S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -. . . . .. . 9-6.0 SAF ETY REQU I R EME NT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.0 PRETEST........................................................... 10 8.0 TE ST PE RFO RMAN CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 Digi tal Isol ator Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2 Anal og Isol a tor Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 H I-P o te n ti al Te s t ( 0C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 HI-P o tenti al Te s t ( AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 Surge Wi ths tand Capabili ty Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.6 An al og Is ol a to r The rmal Dri f t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.7 An al og I sol a to r Li ne a ri ty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 Anal og Isol a to r Power Supply Dri f t. . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.9 Analog Isolator Interchannel Effects at Saturation.......... 20 l 1 l REVISION NO. PROCEDURE NO. EIP-24 ! O JOB CODE - S/N PAGE 2 OF 33 FORM E-o36 REV.o, S/81
t TABLE OF CONTENTS (continued) PAGE 8.10 Anal og Isol ato r Fail ure Mode Isol ation. . . . . . . . . . . . . . . . . . . . . . 20 8.11 An al og I s ol a to r B a ndwi dth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.0 P0STTEST.......................................................... 22 10.0 ACCEPTANCE CRITERI A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.0 RETEST............................................................ 24 12.0 FINAL REVIEW............................................ ......... 25 l REVISION NO. PROCEDURE NO. EIP-24 l 0 " JOB CODE - S/N - PAGE 3 OF 33 l FORM E-034 i REV. O. S/8i '____ w;n._ct - . _ _ _ _ _ . . . _ . - _. .. _ _ . _ . _ _ _ _, . , , , ___ _ _ _ _ ,
t 4 LIST OF FIGURES FIGURE TITLE PAGE 1 Te s t C o n n e c to r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2 Digital Isolator Functional Test Configuration. . ........ . . . . 27 L 3 Digital Isolator Isolation Test Configuration. . . . . . . . . . . . . . . 28 4 Analog Isolator Functional Test Configuration. .. .. ... ... . .. . 29 5 Anal og Isolator Isolation Test Configuration. . . . . . . . . . . . . . . . 30 6 Surge Withstand Transverse Mode Test Configuration.......... 31 7 Surge Withstand Common Mode Test Configuration.............. 32 8 Bandwi dth Tes t Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 l I I l REVISION NO. PROCEDURE NO. EIP-24 0 JOB CODE-S/N PAGE 4 0F 33 FORM E-034 REV.o.5/Si m \
l s LIST OF ATTACHMENTS I TITLE ATTACHMENT
- 1 TEST PROCEDURES TO BE USED 2 TEST EQUIPMENT USE LOG l 3 BURN IN j 4 DIGITAL ISOLATOR FUNCTIONAL TEST 5 NOT USED 6A ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -1, -51, -60 6B ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -2, -52 6C ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -3, -58 .
60 ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -4; -56 6E AN.ALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -5' 6F ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -6 , 6G ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -7 6H ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -8 ' 6J ' ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -9 6K ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -10 6L ANALOG ISOLATOR FUNCTIONAL TEST ASSEMBLY -53 7A DIGITAL ISOLATOR HI-POTENTIAL TEST (DC) 7B ANALOG ISOLATOR HI-POTENTIAL TEST (DC) 8A DIGITAL ISOLATOR.HI-POTENTI.AL TEST (AC) 8B ANALOG ISOLATOR HI-P0TENTIAL TEST (AC) 9 SURGE WITHSTAND CAPABILITY TEST 10 ANALOG ISOLATOR THERMAL DRIFT (3 PAGES) 11 ANALOG ISOLATOR LINEARITY 12 ANALOG ISOLATOR POWER SUPPLY DRIFT (2 PAGES) 13 ANALOG ISOLATOR INTERCHANNEL EFFECT AT SATURATION 14 ANALOG ISOLATOR FAILURE MODE ISOLATION 15 ANALOG ISOLATOR BANDWIDTH l REVISION NO. PROCEDURE NO. EIP-24
- O JOB CODE-S/N PAGE 5 0F 33 l - h
s O - 1.0 PURPOSE This procedure provides a document verifying the performance and electrical isolation of Class 1E analog and digital isolators. Transient voltages usually are capacitively or magnetically coupled from a high voltage source of electrical noise into secondary circuits or control wiring. Since these voltages may appear unsuppressed across connection points of components associated with the protective system, it must be determined that they will not cause a failure or a misoperation of the system. 2.0 RESPONSIBILITIES 2.1 Testing Engineer - It is the responsibility of the test engineer to: (1) Provide the necessary test equipment. (2) Ensure the correct intercor.nection of the test equipment. (3) Perform the test. (4) Document the derived data. (5) Enter the test records in the appropriate project files. (6) Be trained to level II or III per EI QAP 10-2. i
- (7) ~ Notify the QC department of the pending test. ;
1 t REVISION NO. PROCEDURE NO. EIP-24 0 Joe co0E-S/N PAGE 6 OF 33 5EO.5,5Ni" i i l maa a l
s O 2.2 Quality Control Representative l It is the responsibility of the quality control representative to: (1) Verify test is conducted per the procedure. (2) Verify data taken. (3) Verify all equipment used has a current and valid calibration sticker or certificate. (4) Verify proper disposition and storage of test records. (5) Obtain and maintain the test record copy of the procedure, data sheets, and all applicable drawings. 3.0 REFERENCE DOCUMENTS l 3.1 Required Documents i Use the latest revision of the following documents: i (1) EI Drawing 00798, Quad Class 1E Analog Isolation Amplifier
- As sembly.
j (2) EI Drawing 00796, Class 1E Analog Isolation Amplifier Schematic.
- (3) EI Drawing 01026, Class 1E Digital Isolator Amplifier Assembly j
(4) El Drawing 01030, Class 1E Digital Isolator Amplifier Schematic. 4 REVISION NO. PROCEDURE NO. ( a p_n 0 JOB CODE - S/N PAGE 7 OF 33 EEv"o,'s)E"
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i 4 s . 3.2 Other References (1) IEEE Standard Guide, "IEEE 381-1977, Standard Criteria for Type Tests of Class 1E Modules Used in Nuclear Power Generating Stations". (2) IEEE Standard Guide, "IEEE 467-1980, Standard Quality Assurance Program Requirements for the Design and Manufacture of Class 1E Instrumentation and Electric Equipnent for Nuclear Power Gener-ating Stations". (3) IEEE Standard Guide, "IEEE 472-1974, Guide for Surge Withstand Capability (SWC) Tests ( ANSI C 37.90-1978)". 3.3 Test Procedures Used - The tests to be used are job specific. The tests to be run will be speci-fled by the program manager and listed with applicable attachments on Attachment 1. 3.4 Procedure Docunentation Attachments used will (when completed) become part of the test procedure documentation. They will be incorporated into the test record copy of the test and submitted to project management for final review. 4.0 TEST EQUIPMENT REQUIRED (1) Hipot Tester, Hipotronics Model HD125 or equivalent (2) Digital Multimeter (DMM), Fluke Model 8000A or equivalent (3) Dual Power Supply i 15 VDC output (4) 5-Yolt Power Supply REVISION NO. PROCEDURE NO. n p_24 0 JOB CODE-S/N PAGE 8 OF 33 IiE7o,5N?'
t (5) 0-150 VOC Power Supply (6) Surge Transie'nt Generator, Velonex Model 510 or equivalent (7) Systen Calibrator, Fluke 382A or equivalent (8) 4-Card Isolator Test Fixture (9) Test Connector, EI (see Figure 1) (10) Isolator Frame Assembly, P/N 00645-1 or P/N 01000-1 (11) Variac - 120 VAC (12) Test Leads as Required , (13) Oscilloscope, Tektronics 465A or equivalent 2 MHz Bandwidth Minimum, with External Trigger (14) Function Generator, Square Wave, Exact 734 or equivalent 5.0 TEST SIGNAL CHARACTERISTICS 5.1 Hi-Potatial Isolation Test 5.1.1 Peak Voltage: 3 KVOC, for 15 seconds 5.1.2 Peak Voltage: 1.5 KVAC, 60 Hz for One Minute 5.2 Digital Isolator Test (1) Input voltages as specified on the data sheet. REVISION NO. PROCEDURE NO. EIP-24 0 PAGE 9 0F 33 JOB CODE - S/N f M -f2 b
4 5.3 Analog Isolator Test (1) Input voltages or current as specified on the appropriate data sheet. l l 5.4 Surge Withstand Test l (1) Peak Voltage: 2.5 KV. (2) Frequency: 1.0 to 1.5 MHz (no adjustment) . (3) Waveshape: First half of cycle to be full peak voltage, then envelope decays to 50% of the crest value of the first peak in not less than six usec from the start of the wave (no adjustment). (4) Repetition: The test wave shall be applied to the test specimen 60 times per second for two seconds. (5) Source Impedance: 150 ohms. 6.0 SAFETY REQUIREMENTS All safety precautions as noted in the operating manual of the Hipotronics hipot tester will be adhered to. All safety precautions as noted in the operating manual of the Velonex Surge Transient Generator will be adhered to. Caution: Lethal voltage will be present during the performance of these tests. 7.0 PRETEST (1) Fabricate test connector per Figure 1 (if needed). REVISION NO. PROCEDURE NO. rip _24 s 0 JOB CODE - S/N PAGE 10 OF 33 rev"o,1;a"
(2) Remove all keys from edgeboard connectors in prototype isolator frame (if used). (3) Record all test equipment used on Attachment 2. (4) Connect +5 V and 115 V power to isolator frame per Figure 1. , (5) Adjust the +5-V power supply for 5 V t 10 mV. (6) Adjust the 115-V power supply for t15 Y t 10 mV. (7) Allow all parts to operate for burn-in time specified on Attach-ment 3. (8) Record serial nunbers of each group. - 8.0 TEST PERFORMANCE 8.1 Digital Isolator Functional Test (1) Install digital isolator cards in the isolator frame. Record the , serial numbers of the installed cards on the data sheet ( Attach-ment 4). (2) Connect a voltmeter and the calibrator to the test connector in accordance with Figure 2. (3) Turn on the 5-volt power supply. (4) Raise the calibrator voltage until the output voltmeter reads: 1 Y t 0.05 Y. Record the calibrator output voltage on the data sheet. 4 i l l REVISION NO. PROCEDURE NO. EIP-24 ' 0 JOB CODE -S/N PAGE 110F 33 l
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(5) Raise the calibrator' voltage until the output voltmeter reads 3.8 Y t 0.05 V. Record the calibrator output voltage on the data sheet. l (6) Raise the calibrator voltage to 48 Y t 0.1 V. Record the output l voltmeter reading on the data sheet. (7) Repeat (2) through (6) for the remaining channels for outputs as listed on Figure 2. (8) Repeat steps (2) through (7) for all of the cards. 8.2 Analog Isolator Functional Test (1) Record the serial numbers of the installed cards on the data sheet ( Attachment 6). (2) Connect the output of the 115-Y power supply to the test connec-tor per Figure 4. (3) Turn on the 115-V power supply to the isolator frame and allow 10 minutes for warmup. (4) Connect the test connectors to appropriate J1- and J0- connectors on the isolator frame. (5) Turn on the system calibrator and adjust the output for " INPUT LOW" as specified on the data sheet 10.1%. (6) Adjust the "zero" potentiometers on cards 1 and 2 for " OUTPUT LOW" as specified on the data sheet 10.1% on channels 1 through 4 of each card. (7) Adjust the system calibrator output for " INPUT HIGH" as specified on the data sheet 10.1%. REVISION NO. PROCEDURE NO. np_n 0 JOB CODE - S/N PAGE 12 OF 33 av"o,1;#i
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(8) Adjust the " GAIN" potentiometers on cards 1 and 2 for output as specified on the data sheet 10.1% on channels 1 through 4 of each card. (9) Repeat steps (5) through (8) as required, to verify that both adjustments will reach their final desired values. (10) Record the output data on the data sheet. (11) Turn off the dual power supply. J 8.3 Hi-Potential Test (DC) CAUTION: Lethal voltage will be present during the performance of the
- following steps: -
(1) Record the serial numbers of the installed cards on the data sheet ( Attachment 7). (2) Connect the Hipot Tester to all channels of both cards per Figure 3 (for digital isolators) or Figure 5 (for analog isolators.) i (3) Turn on the Hipot Tester and set the " Raise Voltage" control to 0. 1 (4) Set up the Hipot Tester per the characteristics specified in 5.1.1. (5) Gradually increase the voltage applied to the isolator. (6) Stop increasing the voltage when 3 KY is reac:ed or the isolator I breaks down. (7) Record the leakage current on the data sheet. REVISION NO. PROCEDURE NO. EIP-24 0 JOB CODE - S/N PAGE 13 0F 33 AE0"o,1;e"
(8) Turn off the Hipot Tester. . (9) Repeat (1) through (8) for the remaining cards connecting the test connectors to JI2 and J02, JI3 and J03, etc., as required. 8.4 Hi-Potential Test ( AC) CAUTION: Lethal voltage will be present during the performance of the following steps: (1) Recdrd the serial numbers of the installed cards on the data sheet ( Attachment 8). (2) Connect the Hipot Tester to all channels of one of the cards per Figure 3 (for digital cards) or Figure 5 (for analog cards). - (3) Turn on the Hipot Tester and set the " Raise Voltage" control to 0. (4) Set up the Hipot Tester per the characteristics specified in 5.1.2. (5) Gradually increase the voltage applied to the isolator. (6) Stop increasing the voltage when 1.5 KVAC is reached or the isolator breaks down. (7) Let the test run for one minute. 1 (8) Record the leakage current on the data sheet. , (9) Turn off the Hipot Tester. (10) Repeat (1) through (9) for the remaining cards by connecting the test connectors to JI2 and J02, JI3 and J03, etc., as required. i l REVISION NO. PROCEDURE NO. EIP-24 0 PAGE 14 OF 33 JOB CODE- S/N EI-146
8.5 Surge Withstand Capability Test 8.5.1 Pretest Setup
- (1) Plug the Surge Transient Generator and Oscilloscope into a 115-V, 60-Hz source. Activate the power switch on each.
(2) Configure the scope for external trigger. (3) Connect the SCOPE TRIGGER output of the Velonex 510 to the exter-nal trigger input of the oscilloscope per Figure 6. (4) Connect the OUTPUT MONITOR of the Velonex 510 to the scope chan-nel 1 input. (5) Monitor the voltage on the 1 volt /div. scale. . NOTE: The MONITOR OUTPUT of the Velonex 510 presents a 1000:1 attenuated output for scope monitoring. (6) With no output leads attached, configure the Velonex 510 as follows: BURST MODE - Line freq. OUTPUT TIMER MODE - Continuous (for voltage adjustment only) OUTPUT AMPLITUDE - min. SOURCE IMPEDANCE - 150 0 Caution: The following steps will produce lethal voltages on the outputs of the Velonex 510. REVISION NO. PROCEDURE N O. EIP-24 0 JOB CODE - S/N PAGE15 0F 33 rR-xp
(7) With no load connected to the output, simultaneously depress both HV-0N buttons. l l (8) Adjust the AMPLITUDE of the Velonex 510 until 2.5-V peak (2.5-KV output) is displayed on the oscilloscope. (9) Verify that the waveshape displayed has the following character-istics. Record verification on the data sheet ( Attachment 9): Peak Amplitude - 2.5 KV peak Frequency - 1.0 to 1.5 MHz Fall Time - > 6 u see to fall to 50% of peak. (10) Press either HV-0N push button to place the Velonex 510 in standby. - (11) Reconfigure the Velonex 510 as follows: l OUTPUT TIMER MODE - TIMED OUTPUT OUTPUT TIMER DURATION - 2 sec. (12) Reconfigure the scope as follows: INPUT - Alternate (alt) CHANNEL 1 - 1 Volt / Division CHANNEL 2 - 2 Volt / Division , SWEEP - 2 us/ Division TRIGGER - External, Positive Level and Slope (13) Connect the isolator power supply to the test connector in accor-dance with Figure 1. i REVISION NO. PROCEDURE NO. ng_n O Joe CODE-S/N PAGE16 0F 33 l Ie0"o.i;e'*
i l (14) Record the serial numbers of the cards on the data sheet. (15) Insert the card to be tested into the test connector. Perform a functional test on the selected cards per the appro-(16) priate section of this procedure. (17) Connect the Velonex 510 output leads (Caution: verify the unit is in standby) to the test connector in accordance with Figure 6. (18) Connect Channel 2 of the oscilloscope to the test connector in I accordance with Figure 6.
, (19) QC Representative verify all test connections and initial appro-priate column on data sheet. -
8.5.2 Test Performance (20) Turn on the isolator power supply. (21) Visually monitor the oscilloscope. Channel 1 will display the applied surge waveform. Channel 2 will verify the application of the surge waveform to the channel being tested. (22) Depress both HV-0N push buttons of the Velonex 510 simultaneously. (23) Depress the START button of the Velonex 510. (24) Document the application of the SWC Transverse Mode voltage to the test specimen by initialing the appropriate column. (25) Press either of the HV-0N p0sh buttons to place the Velonex 510 in standby. REVISION NO. PROCEDURE NO. gip _24 0 Joe CODE-S/N PAGE 17 OF 33 i 20"o,1;a"
(26) Connect the Velonex output leads and Channel 2 of the oscillo-scope to the test connector in accordance with Figure 7. (27) Repeat steps (19) through (23) . (28) Document the application of the SWC Common Mode voltage to the test specimen by initialing the appropriate column on the data sheet. (29) Press either of the HV-0N push buttons to place the Velonex 510 in standby. (30) Perform a functional test on the channel per the appropriate section of this procedure. Attach a completed copy of the func- ,
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tional test data sheet with pre- and post-SWC test data. , (31) Repeat (17) through (30) for all channels on the card. 8.6 Analog Isolator Thermal Drift
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(1) Record the serial number of the card on the data sheet ( Attach-ment 10). (2) Calibrate the card according to the appropriate functional test of Section 8.2. (3) Set the Environmental Chamber temperature to ambient. Allow card to operate for a period of 20 minutes at the set temperature. (4) Take input and output data for high and low inputs. (5) Repeat steps (3) and (4) for temperatures 5'C,10*C,15'C, and 20*C below ambient. (6) Return the chamber to snbient and repeat step (3). REVISION NO. PROCEDURE N O. EIP-24 0 JOB CODE-S/N PAGE18 0F 33 EI-14 6 _ _, _
(7) Repeat steps (3) through (5) for temperatures 5'C,10*C,15'C, and 20*C above ambient. 8.7 Analog Isolator Linearity 1 (1) Record the serial number of the card on the data sheet ( Attach-ment 11). (2) Calibrate the card according to the appropriate functional test of Section 8.2. (3) Allow card to operate at anbient temperature for 20 minutes. (4) Take readings across the input span in increments of 25% of the span starting at the low end. ' 8.8 Analog Isolator Power Supply Drift (1) Record the serial nunber of the card on the data sheet (Attach-ment 12). (2) Calibrate the card according to the appropriate functional test of Section 8.2. 4 (3) Allow card to operate at ambient temperature for 20 minutes. (4) Adjust the i 15-V power supplies to i 15 VDC i 0.001 VDC. (5) Apply a 50% full scale input to the card using the system calibrator. (6) Record the outputs of each channel. (7) Adjust the +15-VDC power supply to +15.025 + 0.001 VDC. MEVISION NO. PROCEDURE NO. rip _2a 0 JOB CODE-S/N PAGE 19 0F 33 ItkvYoNE
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(8) Record the outputs of each channel. (9) Repeat steps (7) and (8) adjusting the + 15 VDC to + 15.050 VDC. (10) Repeat steps (7) and (8) using +14.975 VDC. (11) Repeat steps (7) and (8) using +14.950 VDC. (12) Return the +15-VDC supply to 15 VDC t .001. (13) Repeat steps (7) to (11) adjusting the VDC supply to the negative values. 8.9 An'alog Isolator Interchannel Ef fects at Saturation (1) Record the serial number of the card on the data sheet ( Attach-ment 13). (2) Calibrate the card according to the appropriate functional test of Section 8.2. (3) Apply a 50% of full scale input to all the channels. Record the outputs. . (4) Continue to apply a 50% of full scale input to three channels and apply a 125% of full scale input to the fourth. Record the outputs of all channels. 8.10 Analog Isolator Failure Mode Isolation (1) Record the serial number of' the card on the data sheet ( Attach-ment 14). (2) Connect a 4.7K n resistor across each of the outputs. i I ! REVISION NO. PROCEDURE N O. EIP-24 0 JOB CODE - S/N PAGE20 0F 33 I h
e.e l (3) Calibrate the card according to the appropriate functional test of Section 8.2. (4) Connect a IK resistor and DMM across the input terminals. 115 volt power is applied for all tests.
. (5) Short across the 4.7K resistor.
(6) Measure the DC voltage at the inputs and record on the data sheet. (7) Remove the resistor, measure the DC voltage at the inputs and . record on the data sheet. (8) Connect 15 VDC across the output terminals with the polarity the same as the output. Measure the DC voltage on the inputs and record on the data sheet. (9) Connect 15 VDC across the output terminals with the polarity opposite the output. Measure the DC voltage on the . input and record on the data sheet. (10) Connect 120 VAC through a 10K. 0, 2-watt resistor to the output terminal s. Measure the AC voltage on the inputs and record on the data sheet. 1 8.11 Analog Isolator Bandwith (1) Record the serial number of the card on the data sheet ( Attach-ment 15) . (2) Calibrate the card according to the appropriate functional test of Section 8.2. . 1 REVISION NO. PROCEDURE NO. EIP-24 0 JOB CODE - S/N PAGE 21 0F 33
. G8 - 140 . _ _
(3) Apply a square wave from the function generator with a magnitude of 100% of full scale input and a duration (T) calculated from the equation below to the inputs of the card.
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T = 10 RC where R and C are taken from El DWG No. 00796. Channel R C 1 R4 + 1/2 R5 C1 2 C R13 + 1/2 R14 4 3 C R22 + 1/2 R23 7 4 R31 + 1/2 R32 C 10 (4) Record the value of RC for the channel on the data sheet. . (5) Connect the oscilloscope and the waveform generator as shown on Figure 8. (6) Adjust the oscilloscope to display the output of the isolator exactly between the 0% and 100% graticle lines. (7) Adjust the sweep to display approximately 5 RC. (8) Enter on the data sheet the time taken for the output to rise from zero to the 63% line on the graticle. (9) Repeat steps (4) through (8) for all channels on the card. 9.0 POSTTEST (1) Remove all test equipment and test leads and fixtures. (2) Return all isolator cards to controlled storage for proper storage. REVISION NO. PROCEDURE NO. EIP-24 0 JOB CODE-S/N PAGE 22 0F 33 EI-846
(3) Submit all data sheets and data acceptance sheets to the respon-sible engineer for review and acceptance or rejection of the tested cards. i
- 10.0 ACCEPTANCE CRITERIA f 10.1 Digital Isolator Functional Test (1) Output less than 1 volt for an input less than 6 volts (DC for -1 assembly, AC RMS for -2 assembly).
(2) Output greater than or equal to 3.8 volts for input voltage greater than 45 volts. 10.2 Analog Isolator Functional Test - i (1) Outputs within 0.1% of output span for inputs at high and low limits of input span. 10.3 HI-Potential Isolation Tests (DC and AC) (1) Leakage current less than 1 uADC at 3 KVDC. (2) Leakage current less than 200 uAAC rms at 1.5 KVAC. 10.4 Surge Withstand Capability Test (1) The channel fails if "zero" and/or " gain" adjustments cannot be made to bring amplifier cutput to within tolerances after SWC test. (2) The channel fails if after the SWC test the output fails to , return to within 0.1% of the output span of the pre-SWC test value. ) REvlSION NO. PROCEDURE NO. E19-24 i I 0 JOB CODE - S/N PAGE2 3 OF 33 IE7o,US"
10.5 Thermal Orif t (1) Output change of less than 0.015% of output span per *C for the range of 10*C to 40*C. 10.6 Lineari ty (1) Output variance from tracking the input is less than 0.1% of the output span. 10.7 Power Supply Drift (1) Output change less than 0.1% of the output span. 10.8 Interchannel Effect at Saturation (1) Output change less than 0.05% of the output span. 10.9 Failure Mode Isolation . (1) Voltage at the input of less than 0.01% of input span. 10.10 Bandwidth , (1) Rise time measured (t) within 20% of calculated (RC). 11.0 RETEST (1) Any card failing the acceptance criteria shall be returned to the card vendor for repair. (2) The repaired card shall be retested according to the appropriate section of this procedure and the retest data recorded on the appropriate data sheet. l REVISION NO. PROCEDURE NO. EIP-24 l 0 JOB CODE-S/N PAGE 24 0F 33 EI-146
P 12.0 FINAL REVIEW All applicable steps of this procedure have been performed as written and all signatures and other verifications are complete. i Test Engineer Signature Date QC Representative Signature Date Qualification level of test engineer verified to level II or III per QAP 10-2. < Functional Manager Signature Date Test procedure approved for use. Project Manager Signature Date . 1 i i l I 1 i REVISION NO. PROCEDURE NO. rrp.24 0 Joe c00E-S/N PAGE 25 0F 33 l l
/ FORM E-034 REV,o, S/81
. _ . . , . - _ , _ _ _ . _ _ _ . . . . ~ . _ - , ~ . - - _ _ . . _ .
! l l
l PS 9 ( + 15v JI 6< c rowan ' x g 7< - surPLv 2 >3 a >s
* '7 5 h9 c > Il
' ' I3 2</ + SV POWER 8 (- 15
>2 1
l ' 9 SUPPLY io % t+ 11 hGr is >0 JO 19 2,'12 OUTPUT i > 65 > 14
- 2. > 2 16 > 16 3
37 ' 57 4 3 'C u "if b55 5$ s 19 20 253 Si , 6 > 6 2i > 49 i 7> 7 22 > 47 8 as l 0'f 9 20 - 9 so 24 2 4543 21 > it 25 > 66 12 26 g54 22 23-{ is 27 52 24> I4 AMP CONNECTOR PARTS NEEDED 28 gso 48 29 i 2F) #5 30 W ! ZG) is PLUG PART AMP No. 38 - 4 27' 7 PS Plug 206708-1 3t N
' 4 2.
'1 29'( f8 Cable Clamp 206966-1 (5) Socket 205090-1 or 1 66602-1 J0 Plug 205839-3 + Cable Clamp 206070-1 (18) Socket 205090-1 or 66602-1 JI Plug 206437-1 Cable Clamp 206512-1 (32) Pin 205089-1 FIGURE 1 Test Connector EIP-24 Page 26 of 33
INPUT SYSTEM CALIBR ATOR E 2 c c.n x .arur im-0 3 oR g VA RI AC s u.a ac ..r,< i.36-o E , 7 8 9 to il 62 13 OUTPUT I"
, 15 16 2
- 17 4
I' 5 g 20 28 7 g 22 23 9 io 24 ll 26 12 13 O O 28 in 29 is 16 DMM ao 17 3I
'8 OUTPUT TEST CONNECTIONS CHANNEL 000 CARD EVEN CARD 1 2 17 2 4 15 3 6 13 4 8 11 5 1 18 6 3 16
, 7 5 14 8 12 7 Com 9 10 t i FIGURE 2 l Digital Isolator Functional Test Configuration l EIP-24 l Page 27 of 33
INPUT HIPOT TESTER 2 m c Ar 3. 0 KV 3 Aca I. 5 x v 4 LOW GND HIGH s c O O O 7 ODD CARD g HIGH 9 to if Il il To ISO L ATOR FRAME 13 19 OUTPUT opD 15 i 2 CARD EVEN l' LOW CARD 17 3 y HIGH Tir g 19 20 6 28 7 8 22 23 9 ' 10 24 EVEN. 25 12 CARD 26 L 27 13 28 19 29 15 2 30 16 38
- #7 32-88 DC Test may be conducted on both cards simultaneously.
- AC Test to be run on one card at a time.
4 i FIGURE 3 Digital Isolator Isolation Test Configuration EIP-24 Page 28 of 33
INPUT SYSTEM E i CAllBRATER 3 E
- s G
i 9 to 11 il 13 19 O U T"PU T
, 15 Ib z
87 3 a II 5 g 20 21 7 g 22 9 , 23 so 24 11 25 iz as i3 @ G 27 sq 28 29
'S DMM ao
' 3i 3 '-
se , TEST CONNECTIONS CHANNEL 000 CARD EVEN CARD INPUT OUTPUT INPUT OUTPUT (+)(-) (+) (-) (+) (-) (+) (-) 1 13 16 8 7 29 32 11 12 2 5 8 6 5 21 24 13 14 3 9 12 4 3 25 28 15 16 4 1 4 2 1 17 20 17 18 Curent
*whi {e vo'.oop
'tage iguts putsmay maybebeconnected connected in serieg1g simultaneous adjustment n para FIGURE 4 Analog Isolator _. Functional Test Configuration EIP-24
\ Page 29 of 33
e INPUT HIPOT TESTER 2 Dc Ar 3.0 xv AC AT 15 KV q LOW GND HIGH 5 OOO c 7 8 cAN to HIGH
- ll I i2 TO ISOLATO R FR AME i3 ODD CARD l'8 OUTPUT '0" i
is 16 i 7 ""E" 37 3 CARD 7 4 HI6H 19 g 20 6 7 zi 9 22 23 9
'O EVEN CARD 25 II LOW 26 12 27 13 28 14 29 15 30 16 17 3I 32-l8 OC Test may be conducted on both cards simultaneously.
AC Test to be run on one card at a time. FIGURE 5 Analog Isolator Isolation Test Configuration l EIP-24 Page 30 of 33
INPUT a HIG H C SWC TESTER LOW C 4 MO N. SYNC 5 O O c 8 i2 13 19 OUTPUT i5 is 2 C 17 3 89 y 19 5 20 4 21 7 22 8 23 9 10 24 25 it O O SYNC 26 C H. 8 12 27 23_ ca 2 SCOPE 28 I4 O 29 15 3 86 (Analog Channel Shown)
,' g DIGITAL ISOLATOR CHANNEL ODD CARD EVEN CARD
(+)IN(-) OUTPUT (+)IN(-) OUTPUT 1 1 9 2 17 25 17 2 2 10 4 18 26 15 3 3 11 6 19 27 13 4 4 12 8 20 28 11 Analcg Isolator ' Inputs and Outputs listed on Figure 7. l f 3 14 7 7 15 5 23 31 8 8 16 7 24 32 12 Com 9- 10 FIGURE 6 Surge Withstand Capability Transverse Mode Test Configuration EIP-24
+.- _ - -,
7 1 INPUT HIG H C I,( i SWC TESTER
'o* C '(
- mon. $YNC 5 O O c 8
9 to Il i2 13 OUTPUT PS , 19 55
, 8s i' 2 C 17 3
a
'ir 19 5
4 20 28 7 8 22
- - 9 23 to 24 ii O OSYNC 25
,2 cw. i 26 CH.2 22 13 O
SCOPE 28 in 2' is ss 30
,7 (Analog Channel Shown)' 3 is ANALOG ISOLATOR 31 CHANNEL ODD CARD EVEN CARD
(+)IN(-) (+)00T(-) (+)IN(-) (+)0VT(-) 1 13 16 8 7 29 32 11 12 Digital Isolator 2 5 8 6 5 21 24 13 14 Inputs and 3 9 12 4 3 25 28 15 16 Outputs listed 4 1 4 2 1 17 20 17 18 on Figure 6. '~ FIGURE 7 - Surge Withstand Capability Coninon Mode Test Configuration EIP-24 Page 32 of 33
e INPUT WAVEFORM 2
- s 3 GENERATOR g 4 s
G 7 8 9 io 11 il 13 OUTPUT '" 15 2-A hINPUT O gygg is y q T a SCOPE I' 5 q 20 28 7 g 22 23 9 no t o o y;- - - - - ,_ - - _ _ _ _ - - - - - _ - - l 24 11 l 25 26 iz I
,3 ox---__ --- i __-____-___-_--t 27 I
l 28 in l ! 29 15 l l l 3 is l 17 l l o v. 32 s .-----r------------------I pt3 [ j< SRC M See Figure 4 for Test Connections Table FIGURE 8 Analog Isolator Bandwidth Test Configuration r<su r m &wt JELMLW
TEST PROCEDURES TO BE USED Attachment Test Section Ntaber Nunber Quantity l i l I I j l t i Program Manager Date j l 1 i l ! l l l l l l Attachment 1 l l 120-2 EIP-24 1 of 1 l . _ . . -
-1 TEST EQUIPMENT USE LOG Date Test Engineer QCR Calibration Item /Model Serial No. Date Used For Tests 2
Attachment 2 120-2 EIP-24 1 of 1
-4 *
)
l BURN-IN Date Test Engineer QCR 115-Volt DC Power Supply used: MODEL S/N
+5-Volt DC Power Supply Used: MODEL S/N Isolator Frame Used: MODEL S/N Isolation Amplifier Printed Circuit Boards Installed Slot Model Serial Number 1
2 3 4 5 6 7
< 8 9
10 11 12 13 14 15 16 17 - 18 19 20 21 22 23 24 Burn-in time Specified Actu11 Attachment 3 120-2 EIP-24 1 of 1
~~
l e FUNCTIONAL TEST DATE: TEST ENGINEER: QCR DIGITAL ISOLATOR DATA SHEET 01026-X Sht of Card Card Output Input to Get Output Slot S/N Channel 0 V in 1 Y out 3.8 Y out 48 V in QCR 1
, 2 3
Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 Rejected 5 6 7 8 Attachment 4 120-1 EIP-24 1 of 1
FUNCTIONAL TEST DATE: TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-1, -51, -60 Low 0V 0V High 51 mVDC 51 mVDC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR 1
2 '
> Accepted 3 Rejected 4 1
2 Accepted 3 - Rejected 4
- 1 2
Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 Accepted 3 Rejected 4 1 2 Accepted 3 i Rejected 4 I 1 2 Accepted 3 Rejected 4 Attachment GA 120-2 EIP-24 1 of 1
o FUNCTIONAL ~ TEST DATE: TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-2, -52 Low 0V 0V High 1 VDC 51 mVDC Sht of Card Card Output Voltage Slot S/N CMnnel Low High QCR 1
2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 - 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 - . Rejected 4 i l Attachment 6B 120-2 EIP-24 1 of 1
FUNCTIONAL TEST DATE: TEST ENGIMEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications 4 Assembly No. Input Output
-3, -58 Low 0V 0V 4 High 10 VDC 10 VOC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR 1
2 4 Accepted 3 Rejected 4
- 1 i 2 Accepted 3 ,
Rejected 4 1 2 i Accepted 3 Rejected 4 1 2 Accepted 3 Rejected _ 4 1 2 ! Accepted 3 Rejected 4 1 1 2 Accepted 3 I Rejected 4-2 1 2 Accepted 3 Rejected 4 i 1 2 Accepted 3 Rejected 4 i l Attachment 6C i 120-2 EIP-24 1 of 1 l . . . - , - . - - - . . -.-
~
FUNCTIONAL TEST l DATE-1 TEST ENGINEER-QCR l 1 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-4, -56 Low 4 mADC 0V High 20 mADC 10 VDC Sht of Card Card Output Voltage l Slot S/N Channel Low Hi gh. QCR 1
2 . Accepted 3 Rejected '4 1 2 Accepted 3 Rejected 4 {- Accepted 3 Rejected 4 l 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 i l l i 1 2 l Accepted 3 i 1 Rejected 4 1 i 2 l Accepted 3 l Rejected 4 i ! l l 1 2 1 Accepted 3 j Rejected 4 Attachment 60 120-2 EIP-24 1 of 1
I . FUNCTIONAL TEST DATE: TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-5 Low 0 mAAC 0 VAC High 50 mAAC 1.3 VAC Sht of Output Voltage Card Card Slot S/N Channel Low High QCR . >
1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected /, 1 2 ~ Accepted 3 Rejected 4 i 1 2 Accepted 3
; Rejected 4 1
2 Accepted 3 Rejected 4 1 2-Accepted 3 Rejected 4 1 2 ! Accepted 3 Rejected 4 1 . 2 - Accepted 3
- Rejected 4 l
l l Attachment 6E i 120-2 EIP-24 1 of 1 l .
~
FUNCTIONAL TEST DATE: TEST ENGINEER: QCR : l 00798 ANALOG ISOLATOR DATA SHEET i Specifications l Assembly No. Input Output
-6 Low 0 VAC 0 VAC High 150 VAC 3.5 VAC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR 1
2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 i 1 l 2 Accepted ? ~ Rejected 4 Attachment 6F 120-2 EIP-24 1 of 1
I
~
. , FUNCTIONAL TEST
. DATE:
1 TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-7 Low 0 VDC 0 VDC High 150 VDC 10 VOC Sht of i Card Card Output Voltage Slot S/N Channel Low High QCR j
1 2 Accepted 3 Rejected 4 1 2 Accepted 3 j Rejected 4 1 2 Accepted 3 i Rejected 4 e 1 2 i Accepted 3 j Rejected 4 i 1 2 Accepted 3 Rejected 4 1 2 , Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 l 2 ) Accepted 3 Rejected 4-l Attachment 6G i 120-2 EIP-24 1 of 1 l
. . -. _ .-- - - - - . - . - . . -l
~ . , FUNCTIONAL TEST DATE:
TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
, -8 Low 0V 0V I -High 10 V PULSE 10 V PULSE Sht of i Card Card Output Voltage 4 Slot S/N Channel Low High QCR 4 1
- 2 Accepted 3 Rejected 41 1-2 Accepted 3
- Rejected 4 1
2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 4 2 Accepted 3 .
- Rejected 4
! 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 1 2
- Accepted 3 j Rejected 4 l
Attachment 6H 120-2 EIP-24 1 of 1 [
. . = , - - . - - - __
FUNCTIONAL TEST-DATE: TEST ENGINEER: j QCR _ 00798 ANALOG ISOLATOR DATA SHEET i Specifications , Assembly No. Input Output . -9 Low 4 mADC 0 VDC High 20 mADC 1 VDC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2
; Accepted 3 Rejected 4 i 1 2
Accepted 3
- Rejected 4 1
2 Accepted 3 Rejected 4 1 2 Accepted 3 i Rejected 4 1 1 2 Accepted 3 Rejected 4 , 1 2 Accepted 3 Rejected 4' Attachment 6J 120-2 .EIP-24 1 of 1
j ..
. FUNCTIONAL TEST DATE:
TEST ENGINEER: QCR 00798 ANALOG ISOLATOR DATA SHEET Specifications Assembly No. Input Output
-10 Low 0V 0V High 51 mVDC 1 VDC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR l 1
! 2 j Accepted 3 Rejected 4 i l 1 ! 2 Accepted 3 Rejected 4 1 1 2 i Accepted 3 - i Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 l 1 i 2 Accepted 3 Rejected 4 1 2 ! Accepted 3 Rejected 4 l l 1 2 Accepted 3 Rejected 4 Attachment 6K 120-2 EIP-24 1 of 1
FUNCTIONAL TEST DATE: TEST ENGINEER: i QCR 00798 ANALOG ISOLATOR DATA SHEET ) Specifications i Assembly No. Input Output
-53 Low 0V 0V
' High 100 mVDC 1 VDC Sht of Card Card Output Voltage Slot S/N Channel Low High QCR 1 2 Accepted 3 i Rejected 4 1 2 ! Accepted 3 i Rejected 4 1 2 3 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 j 2 ! Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 i 1 2 Accepted 3 Rejected 4 1 Attachment 6L 120-2 EIP-24 1 of 1
t HI-POTENTIAL TEST (DC) DATE: TEST ENCINEER: QCR + DIGITAL ISOLATOR DATA SHEET 01026-1 or 01026-2 Sht of Card Card Leakage Current Slot S/N Channel 3 KV QCR i 1 2 3 Accepted 4 Rejected 5 6 7 8 1 1 2 3 Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 Rejected 5
! 6 7
8 1 2 3 Accepted 4 Rejected 5 6 7 8 Attachment 7A 120-2 EIP-24 1 of 1
~
l
. 1 HI-POTENTIAL TEST (DC) l i PROCEDURE NO. DATE: i
, REV. TEST ENGINEER: EI JOB NO. QCR ANALOG ISOLATOR 00798-X DATA SHEET Sht of i Card Card Leakage Current Slot S/N Channel 3 KV QCR 1 1 2 Accepted 3 Rejected 4 1 2 , Accepted 3 Rejected 4 1 2 Accepted 3 Rejected 4 I 1 l 2 Accepted 3 Rejected 4 1 2 Accepted 3 i Rejected 4
.1 2 1 , Accepted 3 Rejected 4 1
2 Accepted 3 Rejected 4 1 + 2 Accepted 3 ! Rejected 4 Attachment 7B 120-2 -- . - . . EIP-24 1 of 1
l
. l l
HI-P0TENTIAL TEST (AC) l DATE: l TEST ENGINEER: QCR j DIGITAL ISOLATOR DATA SHEET 01026-1 or 01026-2 Sht of l Card Card Leakage Current Slot S/N Channel 1.5 KVAC QCR 1 2 3 Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 - Rejected 5 6 7 8 1 2 3 Accepted 4 Rejected 5 6 7 8 1 2 3 Accepted 4 i Rejected 5 l 6 l 7 l 8 l Attachment 8A 120-2 EIP-24 1 of 1
, HI-POTENTIAL TEST (AC) DATE: TEST ENGINEER: QCR ANALOG ISOLATOR 00798-X DATA SHEET Sht of Card Card Leakage Current Slot S/N Channel 1.5 KVAC QCR 1 2 Accepted 3 Rejected 4 1 1 2 1 Accepted 3 Rejected 4 1 2 1 Accepted 3 Rejected 4 1 1 2 i Accepted 3 Rejected 4 l 1 j 2 Accepted 3 Rejected 4 1 > 2 Accepted 3 Rejected 4 1 2 Accepted 3 ! Rejected 4 m 1 2 Accepted 3 Rejected 4 i Attachment 88 l l 120-2 EIP-24 1 ef 1- !
= - , _ . . . - .- .. .. . . _ - _ _ ._. -. ._.
i SURGE WITHSTAND CAPABILITY TEST
, DATE:
TEST ENGINEER: CARD TYPE QCR: WAVESHAPE VERIFICATION QCR Sht of TRANSVERSE MODE S.W.C. TEST QCR QCR PRE-SWC TEST CARD S/N CHANNEL CONNECTIONS OK TEST RUN FUNCTIONAL OK i l I COMMON MODE S.W.C. TEST QCR QCR POST-SWC TEST CARD S/N CHANNEL CONNECTIONS OK TEST RUN FUNCTIONAL OK l i i i i i ! l l l Attachment 9 l 120-2 - . - - _.. . . _ _ EIP-24 1 of 1
. - - _ _ - ~ _ _ _ . . _ . _ _ __ . .. . . _ _ _ . . _ . _ . _ _ _ _
t THERMAL DRIFT DATE: CARD TYPE TEST ENGINEER:
!' CARD S/N QCR:
i Sht of i Temp ( ) *C (Ambient) i Input low Output Input High Output QCR , i CH1 CH2 CH3 CH4 f Temp ( ) *C for a period of CH1 3 CH2 CH3 CH4 Temp ( ) *C for a period of CH1 CH2 CH3 CH4 l ) Temp ( ) *C for a period of i i CH1 CH2 CH3 CH4 Temp ( ) *C for a period of 4 CH1 CH2 CH3 CH4 l l l 1 I i ! Attachment 10 f i- Rflibe 6J040 w J
l _T_HERMAL DRIFT CARD S/N Sht of Temp ( ) 'C ( Ambient) Input low Output Input High Output QCR CH1 CH2 CH3 CH4 Temp ( ) *C for a period of . CH1 CH2 CH3 CH4 Temp ( ) *C for a period of } CH1 CH2 CH3 CH4 Temp ( ) 'C for a period of CH1 CH2 CH3 CH4 Temp ( ) *C for a period of . ! CH1 < CH2 !- CH3 CH4 'I l 4 4 L l l l I Attachment 10 33- IU@-24 .2 of 3
- THERMAL DRIFT CARD S/N Sht of Temp ( ) *C (Ambient)
Input low Output Input High Output QCR CH1 CH2 CH3 CH4 1 1 I l i i l r 1 i Attachment 10 120-2 EIP-24 3 of 3
LINEARITY DATE:- TEST ENGINEER: CARD TYPE QCR: CARD S/N Sht of
-Minimum Input Input- Output QCR CH1 CH2 CH3 CH4 25% of Maximum Input Input Output QCR CH1 CH2 CH2 CH4 ,
t 50% of Maximum Input
- Input Output QCR I
CH1 CH2 CH3 _ CH4 75% of Maximum Input Input Output QCR CH1 CH2 CH3 CH4
- 100% of Maximum Input Input Output- QCR
- s I 'CH1 ,
CH2 , .CH3 CH4 ', Attachment 11 e _ __MJhR : ET P_-24 . ___ _ .. 1 ___ 1 of 1
o
} .
b POWER SUPPLY DRIFT DATE: TEST ENGINEER: CARD TYPE QCR: CARD S/N Sht of (Normal) t 15.0 .001 VDC Input Output QCR CH1 CH2 CH3 CH4
+15.025 VDC Input Output QCR CH1 --
CH2 CH3 CH4
+15.050 VDC Input Output _ QCR CH1 CH2 CH3 CH4
+14.975 VDC Input Output QCR CH1 CH2 CH3
[ CH4
+14.950 VDC Input Output QCR CHI CH2 CH3 CH4 l Attachment 12 l . N &-R [150 m w.
1 POWER SUPPLY DRIFT CARD S/N Sht; of ;, i
-15.025 VDC Input Output , OCR, CH1 _
CH2 CH3 CH4
-15.050 VDC Input Output QCR CH1 4
CH2 - CH3 CH4
-14.975 VDC Input Output QCR CH1 CH2 CH3 CH4
-14.950 VDC 9 Input Output 20CR CH1 CH2 CH3 CH4 .
1 t i 1
../ .
attachment 12 , m -.. rmnat vu;as
INTERCHANNEL EFFECTS AT SATURATION ! DATE: TEST ENGINEER: CARD TYPE QCR:
- CARD S/N Sht of 50% of Full Scale Input Output QCR CH1 CH2
-CH3 CH4
] 125%'of Full Scale i Input Output QCR CH1 CH2 CH3 CH4 6 J i , g At &hment 13
- I BANDWIDTH DATE:
TEST ENGINEER: l CARD TYPE QCR: CARD S/N Sht of RC t OCR CH1 CH2 CH3 CH4 j Attachment 15 120-2 EIP-24 1 of 1
~
) ,
BANDWIDTH DATE: TEST ENGINEER: CARD TYPE QCR: f CARD S/N Sht of 4 RC t QCR CH1 CH2 CH3
~~
CH4 1 O 120-2 Attachment 15 EIP-24 ' 1 of 1
. . . _ . - . . , _ .. . . . _ _ - . _ - - .-}}