ML18142A112

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Rev B to Acceptance Test Procedure ATP443, CD173-Q2 High-Gain Carrier Demodulator
ML18142A112
Person / Time
Site: Surry, 05000000
Issue date: 04/17/1981
From: Kamerman L
VALIDYNE ENGINEERING SALES CORP.
To:
Shared Package
ML18130A405 List:
References
ATP443, NUDOCS 8411200441
Download: ML18142A112 (17)
v • d • e


Text

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A(idyNE ENGINEEIIING COIIPOIIATION REVISIONS LTR ECO DESCRIPTION DATE APPROVED A

See DCN 3/23/81 B

See DCN 4/17/81 TITLE CD173-Q2 High-Gain PROD TEST Carrier Demodulator ENGINEERING NUMBER REV QUAL CONTROL ATP443 SHEET 1

DF 12 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303 VEC 304-11/80

(

A(idyNE ENGINl!l!IIINQ COIIPOIIATION 1.0 SCOPE This document defines the Acceptance Test Procedure (ATP) for the CD173-Q2 High-Gain Carrier Demodulator.

The ATP performs functional tests of all operating characteristics.

A sample of the Test Report to be used with this ATP is contained in Appendix A.

2.0 EQUIPMENT REQUIRED Table 1 lists the test equipment required to perform the ATP.

Table 1.

Equipment Required for ATP Description MCl (Test)

Extender Card (MC1-MC170)

Test Cable Transducer Simulator Digital Multimeter (DMM)

Oscilloscope Decade Resistance Box Function Generator*

Frequency Counter Modulator Manufacturer Validyne Validyne Validyne Validyne Data Precision B & K Heath Kit Interstate Hewlett Packard Validyne 3.0 PRELIMINARY PROCEDURE Part No.

or Model 1109 245 1470 IN-17 F47 5314A 1101 3.1 Plug extender card into front panel connector on MCl.

Alternate None None None Validyne 1527 Commercial Equivi:i,lent Commercial Equivalent Commercial Equivalent Commercial Equivalent Commercial Equivalent Validyne 1104 3.2 Refer to figure 1 and set switches and controls on CD173-Q2 as follows:

Switch or Control Setting GAIN (R30)

Full CW 2/4 (S1B) 2 LO/HI (SlA)

LO MV/V (S3) 10 FILTER (S4) 200 Reference Phase (R15)

Center (0°)

3.3 Plug CD173-Q2 into extender card cable connector.

NUMBER ATP443 SHEET 2

OF 12 8626 WJLBlJR AVFNLJF NORIHBIDGF CA 9l 324

!2l 31 RRS-B488 Telex No 66-l 303 REV I

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MV/V

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FILTER CTI}

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Rll I

BAL:NeE

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Rl2 I

BAL~NeE BREFERENeE PHASE B

R59 22M (REF)

Figure 1.

  • -Re TERMINAL CD173-Q2 Parts Locations RB 150K (REF)

+Re

  • TERMINAL Re

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12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 Re TERMINAL Ei ffl z Cl i RI :I-*

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AlidyNE ENOINEEIH-COllll'OIIATION 3.4 Connect transducer simulator to input connector on rear panel of MCl; set transducer simulator switches as follows:.

Switch Polarity X0.1/Xl. 0 Percent(%)

RANGE MV/V PIN 2/0FF/CT PIN 3/0FF/CT Setting

+

Xl.0 0

1 PIN 2 OFF 3.5 If necessary, connect MCi to 115 Vac and press MCl power switch; observe that power-on indicator lights.

4.0 INITIAL TEST SETUP 4.1 Connect DMM, oscilloscope, MCl and CD173-Q2 as shown in figure 2.

MCl (TEST)

TRANSDUCER SIMULATOR EXTENDER

[ rt

( ]-

CARD w

L I OUTPUT A I BLACK i) 0 RED

!COM jo o Hl DMM NOTE:

BOXED CALLOUT lxxxj INDICATES PANEL MARKINGS Figure 2.

Initial Test Setup NOTE:

Unless otherwise indicated, all switches, controls, and test points referred to in the ATP procedures that follow are located on the CD173-Q2; see figure 1 for locations.

NUMBER CD173-Q2 ill]

4) TPl OSCILLOSCOPE
~
@D ATP443 SHEET 4

OF 12 862 6 '.'VILBL.lBAYE~l.lE

  • NORTHRIDGE. CA 91324 e 12131886-8488
  • Iel"x No 65-1303 REV B

-(

AlidyNE ENOINEEIIINQ COIIPOIIATION 5.0 FUNCTIONAL TESTS Perform all tests and in the order given.

5.1 Null Adjustment and Noise 5.1.1 Set vertical input sensitivity of oscilloscope channel 2 to 20 mV/division; adjust Rand C balance controls Rll and Rl2 for minimum signal on oscilloscope channel 2 connected to AC test point TPl.

5.2.2 Set MV/V switch S3 to 1.

Set DMM to read Vdc, 5.1.3 Adjust Rand C balance controls Rll and Rl2 for minimum signal at AC test point TPl; adjust R60 for 0.000(+/-0.005)V DC output on DMM.

5.1.4" Output noise level observed on oscilloscope channel 1 should be less than or equal to.20 mV peak-to-peak; indicate acceptance on test report with checlanark.

5.1.5 Set MV/V switch S3 successively to 2.5, 5, 10, 25, and 50; at each position the maximum output indication on the DMM should be 0.000(+/-0.030)V DC.

Indicate acceptance on tesE report with checkmark.

5.2 Common Mode Adjustment 5.2.1 Set tr~nsducer simulator switches as follows:

Switch Percent(%)

RANGE MV/V

.PIN 2/0FF/CT PIN 3/0FF/CT Setting 0

40 PIN 2 PIN 3 5.2.2 Set MV/V switch S3 to 1, and 2/4 switch SlB to 4.

5.2.3 Adjust R balance control Rll for 0.000(+/-0.005)V DC output on DMM.

5.2.4 Set transducer simulator percent (%) switch to 100.

5.2.5 Adjust CM ADJ control R5 for 0.000(+/-0.005)V DC output on DMM.

5.2.6 Repeat steps 5.2.1, 5.2.3, 5.2.4, and 5.2.5., if necessary to make sure DMM output is 0.000+/-0.005 Vdc.

5.2.7 Set transducer si'!!Ulator ~I~ 3/0~P/CT switch of OPF.

5.3 Maximum Output and Gain 5.3.1 Set transducer simulator percent(%) switch to 25.

5.3.2 Set 2/4 switch SlB to 2.

Set DMM to read Vdc.

NUMBER ATP443 SHEET 5

OF 862~_','.'ILBUR AVENUE

  • NORTHR 0

1DGE. CA 91324 * (213) 886-8488

  • Telex No. 65-1303 12 REV B

(

AlidyNE ENGINEEIIING COlll"ORATION 5.3.3 The output indication on the DMM should be greater than or equal to

+12.000 Vdc: indicate acceptance on test report with checkmark.

5.3.4 Set transducer simulator RANGE MV/V switch to 1 and percent (%) switch to O.

5.3.5 Adjust R balance control Rll for 0.000(+/-0.005)V DC output on DMM.

5.3.6 Set transducer simulator percent(%) switch to 100.

5.3.7 Adjust GAIN control R30 fully CCW; output i~dication on DMM should be

+1.000(+/-0.130) Vdc.

Indicate acceptance on test report with checkmark.

5.3.8 Adjust GAIN control R30 for +10.000(+/-0.005) Vdc output on DMM; output noise level observed on oscilloscope should be less than or equal to 25 mV peak-to-peak.

Indicate acceptance on test report with checkmark.

5.3.9 Perform the steps in table 2 to check maximum output and gain of CD173-Q2; for each step set MV/V switch S3 and transducer simulator RANGE MV/V and*

percent(%) switches as indicated.

Indicate acceptance on test report with checkmark.

Table 2.

Maximum Output and Gain Check CD173-Q2 Transducer Simulator Output Specification Step MV/V(S3)

RANGE MV/V Percent (%)

On DMM (VDC) 1 1

1 100

+10.000+/-0.050 2

2.5 2.5 100

+10.000+/-0.250 3

5 5

100

+10.000+/-0.250 4

10 10 100

+10.000+/-0.250 5

25 40 50

+ 8.000+/-0.200 6

50 40 100

+ 8.000+/-0.200 5.3.10 Set the simulator to 1 mV/V range.

Perform the steps in the following table by setting the percent switch, on the simulator, to 0% and 100% and note the _;r.:~~di~g_s _at each setting of the m.V/V switch (S3) of Cdl73-n2. Call these readings El and E2 re~pectivelv.

The difference hetween F.2 ~;rl F.l should be as given in the following table.

Indicate acceptance with checkmark on test report.

NUMBER ATP443 SHEET 6

OF

_ -~626 WI_L.BUR AVENUE

  • NORTH RIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65*1303 12 REV B

(

AlidyNE ENGINEEIII-COIIPOIIAflON 5.3.10 (Cont'd).

STEP CD173-02 mV{V DMM READING WITH DMM READING WITH SWITCH (S3 0% INPUT 100%* INPUT SETTING El (Vdc)

E2 (Vdc) 1 1

2 2.5 3

5 4

10 5

25 6

so 5.4 Linearity and Symmetry 5.4.1 Set MV/V switch S3 to 10.

5.4.2 Set 2/4 switch SIB to-4.

Set DMM to read Vdc.

5.4.3 Set transducer simulator switches as follows:

SWITCH SETIING RANGE MV/V 10 PERCENT(%)

0 PIN 2/0FF/CT 2

PIN 3/0FF/CT

  • cT NUMBER ATP443 SHEET DIFFERENCE E2 - El (Vdc) 10.000+/-0.010 4.ooo+/-o.roo 2.000+/-0.050 1.000+/-0.025
0. 400+/-0. 010*

0.200+/-0.005 7

OF 12 8626 WILBUR AVENUE I

NOBTHBIDGF CA 91324 e !?13\\ 996 9499 e Teter Mn sc 1303 REV B

AlidyNE ENGINEEIIING COlll"OIIATION 5.4.4 Adjust R balance control Rll for 0.000(+/-0.002)V DC on DMM.

5.4.5 Set transducer simulator percent(%) switch to 100.

5.4.6 Adjust reference phase control R15 for maximum output on DMM.

5.4.7 Set transducer simulator percent(%) switch to O; output indication on DMM should be 0.000(+/-0.002)V DC.

5.4.8 Repeat steps 5.4.4 thru 5.4.6 as necessary to obtain desired readings.

5.4.9 Set transducer simulator percent(%) switch to 100; adjust GAIN control R30 for +10.000(+/-0.002)" Vdc output on DMM.

5.4.10 Perform the steps in table 3 to check linearity and symmetry of CD173-Q2; for each step set transducer simulator polarity and percent(%) switches as indicated, and indicate acceptance on test report with checkmark.

5.5 5.5.1 5.5.2 Table 3.

Linearity and Symmetry Check Transducer Simulator Output Specification Step Polarity Percent (%)

On DMM (VDC) 1

+

0 0.000+/-0.002 2

+

25

+ 2.500+/-0.005 3

+

50

+ 5.000+/-0.005 4

+

75

+ 7.500+/-0.005 5

+

100

+10.000+/-0.005 6

0 0.000+/-0.002 7.'

25

- 2.500+/-0.005 8

50

- 5.000+/-0.005 9

75

- 7.500+/-0.005 10 100

-10.000+/-0.005 4-Arm and High/Low Balance Set transducer simulator switches as follows:

Switch Polarity Percent(%)

RANGE MV/V PIN 2/0FF/CT PIN 3/0FF/CT Setting

+

0 10 PIN 2 CT Set DMM to read Vdc, adjust R balance control Rll for 0.000 (+/-0.001)

Vdc output on DMM.

NUMBER ATP443 SHEET 8

OF 12 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303 REV B

(

AlidyNE ENGINEEIIING COIIPOIIAT10N 5.5.3 Set 2/4 switch SlB to 2, and transducer simulator PIN 3/0FF/CT switch to OFF; output indication on DMM should be 0.000(+/-0.500)V DC.

Indicate acceptance on test report with checkmark.

5.5.4 Set 2/4 switch SlB to 4 and transducer simulator PIN 3/0FF/CT switch to CT.

5.5.5 Set MV/V switch S3 to 25 and LO/HI switchSlA to HI.

5.5.6 Adjust R balance control Rll full CW; output on DMM should be +8.00(+/-0.4)

Vdc.

Indicate acceptance on test report with checkmark.

5.5.7 Set LO/HI switch SlA to LO; output on DMM should be +o.800(+/-0.2) Vdc.

Indicate acceptance on test report with checkmark.

5.5.8 Adjust R balance control Rll full CCW; output on DMM should be -0.800

(+/-0.2) Vdc.

Indicate acceptance on test report with checkmark.

5.6 Calibration Circuit 5.6.1 Set 2/4 switch SlB to 2 and transducer simulator PIN 2/0FF/CT switch to PIN 2, and PIN 3/0FF/CT switch to OFF.

Set DMM to read Vdc.

5.6.2 Set MV/V switch S3 to 10, and adjust R balance control Rll for 0.000

(+/-0.002)V DC on DMM.

5.6.3 Set decade resistance box to 24.9K; connect one lead of decade resistance box to the +Re terminal and the other lead to the unmarked Re terminal on CD173-Q2 (figure 1); the output indication on DMM should not change.

5.6.4 On CD173-Q2, connect pin 28 of connector (figure 1) to ground; the output indication on DMM should be +9.840(+/-0.400) Vdc.

Indicate acceptance on test report with checkmark:

5.6.5 Move the decade resistance box lead from the +Re terminal to the -Re terminal on CD173-Q2 (figure 1); the output indication on DMM should be -9.840(+/-0.400) Vdc.

Indicate acceptance on test report with checkmark.

5.6.6 Remove decade resistance box leads from terminals and the ground from pin 28 of connector.

5.6.7 Disconnect oscilloscope from CD173-Q2.

5.6.8 Pisconnect DMM and transducer simulator from MCl.

5.7 Filter 5.7.1 Connect function generator, modulator, frequency counter, and oscilloscope as shown in figure 3.

NUMBER ATP443 SHEET 9

OF

    • ~* 8626 WILBUR AVENUE
  • NORTHRIDGE CA.91324
  • 12131 886-8488
  • Telex No. 65-1303 12 REV B

FUNCTION GENERATOR I OUTPUT I

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T --

5.7.2 5.7.3 5.7.4 AlidyNE ENGINEERING COIIPOIIATION MODULATOR MCl (TEST)

I INPUT I TEST

(

~ EXTENDER r-CD173-Q2

[ n CABLE ( D CARD LJ I...

l_

I CARRIER I I OUTPUT A I BLACK > > RED

~

G

~

I INPUT I

..., m FREQUENCY COUNTER OSCILLOSCOPE NOTES:

1.

BOXED CALLOVT ~- INDICATES PANEL OR BOARD MARKINGS Figure 3. Filter Test Setup Set oscilloscope for lV/DIV display, external trigger, and DC coupling; set function generator for a 60 Hz, 3V RMS output.

Set CD173-Q2 switches as follows:

15 Hz Test Switch 2/4 (SlB)

LO/HI (SlA)

Setting 4

LO 5.7.4.1 Set FILTER switch S4 to 15 HZ.

5.7.4.2 Set function generator for a 1.5 Hz sinewave output, as indicated on the frequency counter, and adjust modulator output for a 7-division display on oscilloscope.

NUMBER ATP443 SHEET 10 OF 12 8626 WILBU_B_AVENUE ~ORTH RIDGE. ~A_91324 * (2131 886-8488

  • Telex No. 6_5-1 ~0_3 ___ _

REV B

(

L AlidyNE ENGINEERING COIIPO-TION 5.7.4.3 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 15(+/-2)Hz.

Indicate acceptance on test report with checkmark.

5.7.5 45 Hz Test 5.7.5.1 Set FILTER switch S4 to 45 HZ.

5.7.5.2 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 45(+/-7)Hz.

Indicate acceptance on test report with checkmark.

5.7.6 100 Hz Test 5.7.6.1 Set FILTER switch S4 to 100 HZ.

5.7.6.2 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 100(+/-15)Hz.

Indicate acceptance on test report with checkmark.

5.7.7 200 Hz Test 5.7.7.1 Set FILTER switch S4 to 200 HZ.

5.7.7.2 Increase function generator output ~requency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 200(+/-30)Hz.

Indicate acceptance on test report with checlanark.

5.7.8 Disconnect oscilloscope and test cable from MCl.

5.8 Current Consumption 5.8.1 Connect the DMM leads to the MCl +15V current and voltage test jacks (figure 4); set DMM to read DCmA.

5.8.2 Set the MCl +15V I TEST switch (figure 4) to +15; the DMM indication should not exceed 22 mA.

Indicate acceptance on test report with checkmark.

5.8.3 Set the MCl +15V I TEST switch to the unmarked position; disconnect the DMM leads from the MCl.

5.8.4 Connect the DMM leads to the MCl -15V current and voltage test jacks (figure 4).

5.8.5 Set the MCl -lSV I TEST switch (figure 4) to -15; the DMM indication should not exceed 22 mA.

Indicate acceptance on test report with checlanark.

NUMBER ATP443 SHEET 11 OF 12

-~"'.'.l..1:....1 DI 10 A\\IC.. 11 IC e

l\\lnOTUDlnCC Cl\\ 01 "2"'),1 e

1"'>1 "')\\ QQ,C': QJIQD a

T.nl.n.v Al..a Q:C 1 "20'2 REV B

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NOTE :

AlidyNE ENGINEEIIING COIIPOIIATION TEST

  • OUTPUT B

+15

  • MCl TEST

+15V VOLTAGE TEST JACK *

-15V VOLTAGE TEST JACK

1.

CONNECT DMM COM LEAD TO CURRENT TEST JACK AND HI LEAD TO VOLTAGE TEST JACK Figure 4.

MCl (Test) +/-15V Current.Test Switch and Jack Locations 5.8.6 Set the MCl 715V I TEST switch to the unmarked position; disconnect the DMM leads from the MCl.

5.8.7 Unplug CD173-Q2 from extender card cable connector.

NUMBER ATP443 SHEET 12 OF 12 8626 WILBUR AVENUE_* NORTHRIDGE. CA 91324 * (213) 886-8488

  • Telex No. 65-1303 REV B*

(

AlidyNE ENGINEEIIING COII..OIIATION APPENDIX A SAMPLE TEST REPORT NUMBER ATP443 SHEET 1

OF s

AA,FLWJI Rllfl t.Vl=I\\Jll~l'lRTJ.IRIDGF CA 91324 12131 BRS.8488 TpJpx No S5-l 303 REV B

m v~!!~l'~.!

TEST REPORT CD173-Q2 High-Gain ASSY Carrier Demodulator S/0 CUSTOMER W /0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted 5.1 Null Adjustment and Noise 5.1.4 Oscilloscope Indication 5.1.5 DMM Indication S3 at 2.5 S3 at 5 S3 at 10 S3 at 25 S3 at 50 5.3 Maximum Output and Gain 5.3.3 DMM Indication 5.3.7 DMM Indication 5.3.8 Oscilloscope Indication 5.3.9 Table 2 QC Step Indication On 1

2 3

4 DMM DMM DMM DMM NUMBER ATP443 Specification.

~20 mVp-p 0.000 (+/-0.030) Vdc 0.000 (+/-0.030) Vdc 0.000 (+/-0.030) Vdc 0.000 (+/-0. 030) Vdc*

0.000 (+/-0. 030) Vdc

>+12.000 Vdc

+1.000 (+/-0.130) Vdc

~25 mVp-p

+10.000(+/-0.050) Vdc

+10.000(+/-0.250) Vdc

+10.000(+/-0.250) Vdc

+10.000(+/-0.250) Vdc REV B

SHEET 2

OF 5

8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65*1303 vr:f' '1nc:...11,an

(

TEST REPORT CD173-Q2 High-Gain ASSY Carrier Demodulator S/0 CUSTOMER W/0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted Specification.

5.3.9 5.3.10 5.4 5.4.10 oc Table 2 (Continued)

Step Indication On 5

DMM 6

DMM Step Indicat*ion On 1

E2-El 2

E2-El 3

E2-El 4

E2-El 5

E2-El 6

E2-El Linearity and Symmetry Table 3 Step Indication On 1

DMM 2

DMM NUMBER ATP443

+8.000 (+/-0. 200) Vdc

+8.000 (+/-0. 200) Vdc 10.000+/-0.010 Vdc 4.000+/-0.100 Vdc 2.000+/-0.050 Vdc 1.000+/-0.025 Vdc 0.400+/-0.010 Vdc 0.200+/-0.005 Vdc 0.000(+/-0.002) Vdc

+2.500(+/-0.005) Vdc SHEET 3

OF 5

REV B

8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886*8488
  • Telex No. 65-1303

TEST REPORT S/0 W/0 TESTED BY ASSY CD173-Q2 High-Gain Carrier Qemodnlator CUSTOMER SERIAL NO.

DATE Paragraph/Step Accepted 5.4.10 Table 3 (Cont'd).

5.5 Step Indication On 3

4 5

6 7

8 9

10 DMM DMM DMM DMM DMM DMM DMM DMM 4-Arm and High/Low Balance 5.5.3 DMM Indication 5.5.6 DMM Indication 5.5.7 DMM Indication 5.5.8 DMM Indication 5.6 Calibration Circuit 5.6.4 DMM Indication 5*. 6. 5 DMM Indication oc NUMBER ATP443 SHEET Specification *

+5. 000 (+/-0. 005) Vdc *

+7.500 (+/-0.005) Vdc

+10.000 (+/-0.005) Vdc 0.000 (+/-0.002) Vdc

-2.500 (+/-0.005) Vdc

-5.000 (+/-0.005) Vdc

-7.500 (+/-0.005) Vdc

-10.000 (+/-0.005) Vdc 0.000 (+/-0.500) Vdc

+8.000 (+/-0.4) Vdc

+0.800 (+/-0.2) Vdc

-0.800 (+/-0.2) Vdc

+9.840 (+/-0. 400) Vdc

-9.840 +/-0.400 Vdc REV B

4 OF 5

8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488

~

l S/0 W/0 TESTED BY ASSY TEST REPORT CD173-Q2 High-Gain

  • Carrier Demodulator CUSTOMER SERIAL NO.

DATE Paragraph/Step Accepted Specification 5.7 5.7.4.3 5.7.5.2 5.7.6.2 5.7.7.2 5.8 5.8.2 5.8.5 oc VEC :ini; 111An Filter Frequency Counter Indication 15 (+/-2) Hz Frequency Counter Indication 45 (+/-7) Hz Frequency Counter Indication 100 (+/-15)

Frequency Counter Indication 200 (+/-30)

Current Consumption DMM Indication 22 mA max.

DMM Indication 22 mA max.

NUMBER ATP443 SHEET 5

OF 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886*8488
  • Telex No. 65*1303 Hz Hz 5

REV B

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