ML18142A112

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Rev B to Acceptance Test Procedure ATP443, CD173-Q2 High-Gain Carrier Demodulator.
ML18142A112
Person / Time
Site: Surry, 05000000
Issue date: 04/17/1981
From: Kamerman L
VALIDYNE ENGINEERING SALES CORP.
To:
Shared Package
ML18130A405 List:
References
ATP443, NUDOCS 8411200441
Download: ML18142A112 (17)
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A(idyNE ENGINEEIIING COIIPOIIATION REVISIONS LTR ECO DESCRIPTION DATE APPROVED A See DCN 3/23/81 B See DCN 4/17/81 TITLE CD173-Q2 High-Gain PROD TEST Carrier Demodulator ENGINEERING NUMBER REV QUAL CONTROL ATP443 SHEET 1 DF 12 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303 VEC 304-11/80

A(idyNE ENGINl!l!IIINQ COIIPOIIATION

(

1.0 SCOPE This document defines the Acceptance Test Procedure (ATP) for the CD173-Q2 High-Gain Carrier Demodulator. The ATP performs functional tests of all operating characteristics. A sample of the Test Report to be used with this ATP is contained in Appendix A.

2.0 EQUIPMENT REQUIRED Table 1 lists the test equipment required to perform the ATP.

Table 1. Equipment Required for ATP Part No.

Description Manufacturer or Model Alternate MCl (Test) Validyne None Extender Card (MC1-MC170) Validyne None Test Cable Validyne None Transducer Simulator Validyne 1109 Validyne 1527 Digital Multimeter (DMM) Data Precision 245 Commercial Equivi:i,lent Oscilloscope B & K 1470 Commercial Equivalent Decade Resistance Box Heath Kit IN-17 Commercial Equivalent Function Generator* Interstate F47 Commercial Equivalent Frequency Counter Hewlett Packard 5314A Commercial Equivalent Modulator Validyne 1101 Validyne 1104 3.0 PRELIMINARY PROCEDURE 3.1 Plug extender card into front panel connector on MCl.

3.2 Refer to figure 1 and set switches and controls on CD173-Q2 as follows:

Switch or Control Setting GAIN (R30) Full CW 2/4 (S1B) 2 LO/HI (SlA) LO MV/V (S3) 10 FILTER (S4) 200 Reference Phase (R15) Center (0°)

3.3 Plug CD173-Q2 into extender card cable connector.

NUMBER REV ATP443 I SHEET 2 OF 12 8626_WJLBlJR AVFNLJF

  • NORIHBIDGF CA 9l 324 * !2l 31 RRS-B488
  • Telex No 66-l 303

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AlidyNE ENOINEEIH- COllll'OIIATION 3.4 Connect transducer simulator to input connector on rear panel of MCl; set transducer simulator switches as follows:.

Switch Setting Polarity +

X0.1/Xl. 0 Xl.0 Percent(%) 0 RANGE MV/V 1 PIN 2/0FF/CT PIN 2 PIN 3/0FF/CT OFF 3.5 If necessary, connect MCi to 115 Vac and press MCl power switch; observe that power-on indicator lights.

4.0 INITIAL TEST SETUP 4.1 Connect DMM, oscilloscope, MCl and CD173-Q2 as shown in figure 2.

MCl (TEST)

TRANSDUCER SIMULATOR

- EXTENDER ,... CD173-Q2

[w rt ( ]- ,-

CARD ill]

L I OUTPUT A I

-- -- 4) TPl BLACK i) 0 RED OSCILLOSCOPE

!COM jo o Hl  :~

@D DMM '

NOTE: BOXED CALLOUT lxxxj INDICATES PANEL MARKINGS Figure 2. Initial Test Setup NOTE: Unless otherwise indicated, all switches, controls, and test points referred to in the ATP procedures that follow are located on the NUMBER REV CD173-Q2; see figure 1 for locations. ATP443 B SHEET 4 OF 12

_862_6_'.'VILBL.lBAYE~l.lE

  • NORTHRIDGE. CA 91324 e 12131886-8488
  • Iel"x No 65-1303

AlidyNE ENOINEEIIINQ COIIPOIIATION 5.0 FUNCTIONAL TESTS Perform all tests and in the order given.

5.1 Null Adjustment and Noise 5.1.1 Set vertical input sensitivity of oscilloscope channel 2 to 20 mV/division; adjust Rand C balance controls Rll and Rl2 for minimum signal on oscilloscope channel 2 connected to AC test point TPl.

5.2.2 Set MV/V switch S3 to 1. Set DMM to read Vdc, 5.1.3 Adjust Rand C balance controls Rll and Rl2 for minimum signal at AC test point TPl; adjust R60 for 0.000(+/-0.005)V DC output on DMM.

5.1.4" Output noise level observed on oscilloscope channel 1 should be less than or equal to .20 mV peak-to-peak; indicate acceptance on test report with checlanark.

5.1.5 Set MV/V switch S3 successively to 2.5, 5, 10, 25, and 50; at each position the maximum output indication on the DMM should be 0.000(+/-0.030)V DC.

Indicate acceptance on tesE report with checkmark.

5.2 Common Mode Adjustment 5.2.1 Set tr~nsducer simulator switches as follows:

Switch Setting Percent(%) 0 RANGE MV/V 40

.PIN 2/0FF/CT PIN 2 PIN 3/0FF/CT PIN 3 5.2.2 Set MV/V switch S3 to 1, and 2/4 switch SlB to 4.

5.2.3 Adjust R balance control Rll for 0.000(+/-0.005)V DC output on DMM.

5.2.4 Set transducer simulator percent (%) switch to 100.

5.2.5 Adjust CM ADJ control R5 for 0.000(+/-0.005)V DC output on DMM.

5.2.6 Repeat steps 5.2.1, 5.2.3, 5.2.4, and 5.2.5., if necessary to make sure DMM output is 0.000+/-0.005 Vdc.

5.2.7 Set transducer si'!!Ulator ~I~ 3/0~P/CT switch of OPF.

5.3 Maximum Output and Gain 5.3.1 Set transducer simulator percent(%) switch to 25.

-( 5.3.2 Set 2/4 switch SlB to 2. Set DMM to read Vdc. NUMBER REV ATP443 B SHEET 5 OF 12 0

862~_','.'ILBUR AVENUE

  • NORTHR 1DGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303

AlidyNE ENGINEEIIING COlll"ORATION

(

5.3.3 The output indication on the DMM should be greater than or equal to

+12.000 Vdc: indicate acceptance on test report with checkmark.

5.3.4 Set transducer simulator RANGE MV/V switch to 1 and percent (%) switch to O.

5.3.5 Adjust R balance control Rll for 0.000(+/-0.005)V DC output on DMM.

5.3.6 Set transducer simulator percent(%) switch to 100.

5.3.7 Adjust GAIN control R30 fully CCW; output i~dication on DMM should be

+1.000(+/-0.130) Vdc. Indicate acceptance on test report with checkmark.

5.3.8 Adjust GAIN control R30 for +10.000(+/-0.005) Vdc output on DMM; output noise level observed on oscilloscope should be less than or equal to 25 mV peak-to-peak. Indicate acceptance on test report with checkmark.

5.3.9 Perform the steps in table 2 to check maximum output and gain of CD173-Q2; for each step set MV/V switch S3 and transducer simulator RANGE MV/V and*

percent(%) switches as indicated. Indicate acceptance on test report with checkmark.

Table 2. Maximum Output and Gain Check CD173-Q2 Transducer Simulator Output Specification Step MV/V(S3) RANGE MV/V Percent (%) On DMM (VDC) 1 1 1 100 +10.000+/-0.050 2 2.5 2.5 100 +10.000+/-0.250 3 5 5 100 +10.000+/-0.250 4 10 10 100 +10.000+/-0.250 5 25 40 50 + 8.000+/-0.200 6 50 40 100 + 8.000+/-0.200 5.3.10 Set the simulator to 1 mV/V range. Perform the steps in the following table by setting the percent switch, on the simulator, to 0% and 100% and note the _;r.:~~di~g_s _at each setting of the m.V/V switch (S3) of Cdl73-n2. Call these readings El and E2 re~pectivelv. The difference hetween F.2 ~;rl F.l should be as given in the following table. Indicate acceptance with checkmark on test report.

  • NUMBER REV ATP443 B SHEET 6 OF 12

_ -~626 WI_L.BUR AVENUE

  • NORTH RIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65*1303

(

AlidyNE ENGINEEIII- COIIPOIIAflON 5.3.10 (Cont'd).

STEP CD173-02 mV{V DMM READING WITH DMM READING WITH DIFFERENCE SWITCH (S3 0% INPUT 100%* INPUT E2 - El SETTING El (Vdc) E2 (Vdc) (Vdc) 1 1 --- --- 10.000+/-0.010 2 2.5 --- --- 4.ooo+/-o.roo 3 5 --- --- 2.000+/-0.050 4 10 --- --- 1.000+/-0.025 5 25 --- --- 0. 400+/-0. 010*

6 so --- --- 0.200+/-0.005 5.4 Linearity and Symmetry 5.4.1 Set MV/V switch S3 to 10.

5.4.2 Set 2/4 switch SIB to-4. Set DMM to read Vdc.

5.4.3 Set transducer simulator switches as follows:

SWITCH SETIING RANGE MV/V 10 PERCENT(%) 0 PIN 2/0FF/CT 2 PIN 3/0FF/CT *cT NUMBER REV ATP443 B SHEET 7 OF 12 8626 WILBUR AVENUE I NOBTHBIDGF CA 91324 e  !?13\ 996 9499 e Teter Mn sc 1303

AlidyNE ENGINEEIIING COlll"OIIATION 5.4.4 Adjust R balance control Rll for 0.000(+/-0.002)V DC on DMM.

5.4.5 Set transducer simulator percent(%) switch to 100.

5.4.6 Adjust reference phase control R15 for maximum output on DMM.

5.4.7 Set transducer simulator percent(%) switch to O; output indication on DMM should be 0.000(+/-0.002)V DC.

5.4.8 Repeat steps 5.4.4 thru 5.4.6 as necessary to obtain desired readings.

5.4.9 Set transducer simulator percent(%) switch to 100; adjust GAIN control R30 for +10.000(+/-0.002)" Vdc output on DMM.

5.4.10 Perform the steps in table 3 to check linearity and symmetry of CD173-Q2; for each step set transducer simulator polarity and percent(%) switches as indicated, and indicate acceptance on test report with checkmark.

Table 3. Linearity and Symmetry Check Transducer Simulator Output Specification Step Polarity Percent (%) On DMM (VDC) 1 . + 0 0.000+/-0.002 2 + 25 + 2.500+/-0.005 3 + 50 + 5.000+/-0.005 4 + 75 + 7.500+/-0.005 5 + 100 +10.000+/-0.005 6 - 0 0.000+/-0.002 7 .' - 25 - 2.500+/-0.005 8 - 50 - 5.000+/-0.005 9 - 75 - 7.500+/-0.005 10 - 100 -10.000+/-0.005 5.5 4-Arm and High/Low Balance 5.5.1 Set transducer simulator switches as follows:

Switch Setting Polarity +

Percent(%) 0 RANGE MV/V 10 PIN 2/0FF/CT PIN 2 PIN 3/0FF/CT CT 5.5.2 Set DMM to read Vdc, adjust R balance control Rll for 0.000 (+/-0.001)

Vdc output on DMM.

NUMBER REV ATP443 B SHEET 8 OF 12 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303

AlidyNE ENGINEEIIING COIIPOIIAT10N

(

5.5.3 Set 2/4 switch SlB to 2, and transducer simulator PIN 3/0FF/CT switch to OFF; output indication on DMM should be 0.000(+/-0.500)V DC. Indicate acceptance on test report with checkmark.

5.5.4 Set 2/4 switch SlB to 4 and transducer simulator PIN 3/0FF/CT switch to CT.

5.5.5 Set MV/V switch S3 to 25 and LO/HI switchSlA to HI.

5.5.6 Adjust R balance control Rll full CW; output on DMM should be +8.00(+/-0.4)

Vdc. Indicate acceptance on test report with checkmark.

5.5.7 Set LO/HI switch SlA to LO; output on DMM should be +o.800(+/-0.2) Vdc.

Indicate acceptance on test report with checkmark.

5.5.8 Adjust R balance control Rll full CCW; output on DMM should be -0.800

(+/-0.2) Vdc. Indicate acceptance on test report with checkmark.

5.6 Calibration Circuit 5.6.1 Set 2/4 switch SlB to 2 and transducer simulator PIN 2/0FF/CT switch to PIN 2, and PIN 3/0FF/CT switch to OFF. Set DMM to read Vdc.

5.6.2 Set MV/V switch S3 to 10, and adjust R balance control Rll for 0.000

(+/-0.002)V DC on DMM.

5.6.3 Set decade resistance box to 24.9K; connect one lead of decade resistance box to the +Re terminal and the other lead to the unmarked Re terminal on CD173-Q2 (figure 1); the output indication on DMM should not change.

5.6.4 On CD173-Q2, connect pin 28 of connector (figure 1) to ground; the output indication on DMM should be +9.840(+/-0.400) Vdc. Indicate acceptance on test report with checkmark:

5.6.5 Move the decade resistance box lead from the +Re terminal to the -Re terminal on CD173-Q2 (figure 1); the output indication on DMM should be -9.840(+/-0.400) Vdc. Indicate acceptance on test report with checkmark.

5.6.6 Remove decade resistance box leads from terminals and the ground from pin 28 of connector.

5.6.7 Disconnect oscilloscope from CD173-Q2.

5.6.8 Pisconnect DMM and transducer simulator from MCl.

5.7 Filter 5.7.1 Connect function generator, modulator, frequency counter, and oscilloscope as shown in figure 3.

NUMBER REV ATP443 B SHEET 9 OF 12

    • ~* 8626 WILBUR AVENUE
  • NORTHRIDGE CA.91324
  • 12131 886-8488
  • Telex No. 65-1303

AlidyNE ENGINEERING COIIPOIIATION FUNCTION MODULATOR MCl (TEST)

GENERATOR I OUTPUT-I IINPUT I TEST ~ EXTENDER r- CD173-Q2

- [nLJ CABLE (

I... D ( CARD l_

I CARRIER I I OUTPUT A I

~ -

T BLACK > > RED

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I INPUT I FREQUENCY COUNTER m

OSCILLOSCOPE NOTES:

1. BOXED CALLOVT ~ - INDICATES PANEL OR BOARD MARKINGS Figure 3. Filter Test Setup 5.7.2 Set oscilloscope for lV/DIV display, external trigger, and DC coupling; set function generator for a 60 Hz, 3V RMS output.

5.7.3 Set CD173-Q2 switches as follows:

Switch Setting 2/4 (SlB) 4 LO/HI (SlA) LO 5.7.4 15 Hz Test 5.7.4.1 Set FILTER switch S4 to 15 HZ.

5.7.4.2 Set function generator for a 1.5 Hz sinewave output, as indicated on the frequency counter, and adjust modulator output for a 7-division display on oscilloscope.

NUMBER REV ATP443 B SHEET 10 OF 12 8626 WILBU_B_AVENUE ~ORTH RIDGE. ~A_91324 * (2131 886-8488

  • Telex No. 6_5-1 ~0_3___ _ _:

AlidyNE ENGINEERING COIIPO-TION

(

5.7.4.3 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 15(+/-2)Hz.

Indicate acceptance on test report with checkmark.

5.7.5 45 Hz Test 5.7.5.1 Set FILTER switch S4 to 45 HZ.

5.7.5.2 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 45(+/-7)Hz.

Indicate acceptance on test report with checkmark.

5.7.6 100 Hz Test 5.7.6.1 Set FILTER switch S4 to 100 HZ.

5.7.6.2 Increase function generator output frequency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate 100(+/-15)Hz. Indicate acceptance on test report with checkmark.

5.7.7 200 Hz Test 5.7.7.1 Set FILTER switch S4 to 200 HZ.

5.7.7.2 Increase function generator output ~requency until oscilloscope display decreases to 5 divisions; the frequency counter should indicate

  • 200(+/-30)Hz. Indicate acceptance on test report with checlanark.

5.7.8 Disconnect oscilloscope and test cable from MCl.

5.8 Current Consumption 5.8.1 Connect the DMM leads to the MCl +15V current and voltage test jacks (figure 4); set DMM to read DCmA.

5.8.2 Set the MCl +15V I TEST switch (figure 4) to +15; the DMM indication should not exceed 22 mA. Indicate acceptance on test report with checkmark.

5.8.3 Set the MCl +15V I TEST switch to the unmarked position; disconnect the DMM leads from the MCl.

5.8.4 Connect the DMM leads to the MCl -15V current and voltage test jacks (figure 4).

5.8.5 Set the MCl -lSV I TEST switch (figure 4) to -15; the DMM indication should not exceed 22 mA. Indicate acceptance on test report with checlanark.

NUMBER REV ATP443 B SHEET 11 OF 12

-~"'.'.l..1:....1 DI 10 A\IC .. 11 IC e l\lnOTUDlnCC Cl\ 01 "2"'),1 e 1"'>1 "')\ QQ,C':_QJIQD a T.nl.n.v Al..a_ __ Q:C 1 "20'2 _J

AlidyNE

( ENGINEEIIING COIIPOIIATION OUTPUT

  • TEST B
  • +15V VOLTAGE TEST JACK *
  • -15V VOLTAGE
  • +15 TEST JACK NOTE :

MCl TEST

1. CONNECT DMM COM LEAD TO CURRENT TEST JACK AND HI LEAD TO VOLTAGE TEST JACK Figure 4. MCl (Test) +/-15V Current .Test Switch and Jack Locations 5.8.6 Set the MCl 715V I TEST switch to the unmarked position; disconnect the DMM leads from the MCl.

5.8.7 Unplug CD173-Q2 from extender card cable connector.

NUMBER REV ATP443 B*

SHEET 12 OF 12 8626 WILBUR AVENUE_* NORTHRIDGE. CA 91324 * (213) 886-8488

  • Telex No. 65-1303

AlidyNE ENGINEEIIING COII..OIIATION

(

APPENDIX A SAMPLE TEST REPORT NUMBER REV ATP443 B SHEET 1 OF s AA,FLWJI Rllfl t.Vl=I\Jll~l'lRTJ.IRIDGF CA 91324

  • 12131 BRS.8488

m v~!!~l'~.! TEST REPORT CD173-Q2 High-Gain ASSY Carrier Demodulator S/0 CUSTOMER W/0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted Specification.

5.1 Null Adjustment and Noise 5.1.4 Oscilloscope Indication ~20 mVp-p 5.1.5 DMM Indication S3 at 2.5 0.000 (+/-0.030) Vdc S3 at 5 0.000 (+/-0.030) Vdc S3 at 10 0.000 (+/-0.030) Vdc S3 at 25 0.000 (+/-0. 030) Vdc*

S3 at 50 0.000 (+/-0. 030) Vdc 5.3 Maximum Output and Gain 5.3.3 DMM Indication >+12.000 Vdc 5.3.7 DMM Indication +1.000 (+/-0.130) Vdc 5.3.8 Oscilloscope Indication ~25 mVp-p 5.3.9 Table 2 Step Indication On 1 DMM +10.000(+/-0.050) Vdc 2 DMM +10.000(+/-0.250) Vdc 3 DMM +10.000(+/-0.250) Vdc 4 DMM +10.000(+/-0.250) Vdc NUMBER REV ATP443 B QC SHEET 2 OF 5 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65*1303 vr:f' '1nc:...11 ,an

( TEST REPORT CD173-Q2 High-Gain ASSY Carrier Demodulator S/0 CUSTOMER W/0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted Specification.

5.3.9 Table 2 (Continued)

Step Indication On 5 DMM +8.000 (+/-0. 200) Vdc 6 DMM +8.000 (+/-0. 200) Vdc 5.3.10 Step Indicat*ion On 1 E2-El 10.000+/-0.010 Vdc 2 E2-El 4.000+/-0.100 Vdc 3 E2-El 2.000+/-0.050 Vdc 4 E2-El 1.000+/-0.025 Vdc 5 E2-El 0.400+/-0.010 Vdc 6 E2-El 0.200+/-0.005 Vdc 5.4 Linearity and Symmetry 5.4.10 Table 3 Step Indication On 1 DMM 0.000(+/-0.002) Vdc 2 DMM +2.500(+/-0.005) Vdc NUMBER REV ATP443 B oc SHEET 3 OF 5 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886*8488
  • Telex No. 65-1303

TEST REPORT CD173-Q2 High-Gain ASSY Carrier Qemodnlator S/0 CUSTOMER W/0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted Specification

  • 5.4.10 Table 3 (Cont'd).

Step Indication On 3 DMM +5. 000 (+/-0. 005) Vdc

  • 4 DMM +7.500 (+/-0.005) Vdc 5 DMM +10.000 (+/-0.005) Vdc 6 DMM 0.000 (+/-0.002) Vdc 7 DMM -2.500 (+/-0.005) Vdc 8 DMM -5.000 (+/-0.005) Vdc 9 DMM -7.500 (+/-0.005) Vdc 10 DMM -10.000 (+/-0.005) Vdc 5.5 4-Arm and High/Low Balance 5.5.3 DMM Indication 0.000 (+/-0.500) Vdc 5.5.6 DMM Indication +8.000 (+/-0.4) Vdc 5.5.7 DMM Indication +0.800 (+/-0.2) Vdc 5.5.8 DMM Indication -0.800 (+/-0.2) Vdc 5.6 Calibration Circuit 5.6.4 DMM Indication +9.840 (+/-0. 400) Vdc 5*. 6. 5 DMM Indication -9.840 +/-0.400 Vdc NUMBER REV B

ATP443 oc SHEET 4 OF 5 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886-8488
  • Telex No. 65-1303

TEST REPORT CD173-Q2 High-Gain

  • ASSY Carrier Demodulator S/0 CUSTOMER W/0 SERIAL NO.

TESTED BY DATE Paragraph/Step Accepted Specification 5.7 Filter 5.7.4.3 Frequency Counter Indication 15 (+/-2) Hz 5.7.5.2 Frequency Counter Indication 45 (+/-7) Hz 5.7.6.2 Frequency Counter Indication 100 (+/-15) Hz 5.7.7.2 Frequency Counter Indication 200 (+/-30) Hz 5.8 Current Consumption 5.8.2 DMM Indication 22 mA max.

5.8.5 DMM Indication 22 mA max.

NUMBER REV ATP443 B oc SHEET 5 OF 5 8626 WILBUR AVENUE

  • NORTHRIDGE. CA 91324 * (213) 886*8488
  • Telex No. 65*1303
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