ML20235Y889

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Rev 0 to Rept on Response to NRC IE Circular 79-02, Engineering Rept
ML20235Y889
Person / Time
Site: Rancho Seco
Issue date: 09/28/1987
From:
SACRAMENTO MUNICIPAL UTILITY DISTRICT
To:
Shared Package
ML20235Y592 List:
References
ERPT-0229, ERPT-0229-R00, ERPT-229, ERPT-229-R, IEC-79-02, IEC-79-2, NUDOCS 8710200520
Download: ML20235Y889 (48)
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{{#Wiki_filter:_ _ - _ _ _ _ _ _ _ _ __ gk t j .9 I ENGINEERING REF ORT ERPT - 0229 REPORT ON RESPONSE TO NRC IE CIRCULAR 79-02 SACRAMENTO MUNICIPAL UTILITY DISTRICT REVISION 0 SEPTEMBER 28, 1987 Prepared by: BenSupremodb Reviewed by: Ram Gupta /24 Approved by: Noy Basu y pj c-8710200520 071012 PDR ADOCK 05000312 G PDR 1 .l ~ ~Rr ., +:- - c =ypf =~- ~ ~-~~~~;:._:.n~~rw..

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La '1 - se i l TABLE OF CCNTENTS Page I Introduction 1 II Scope 1 III Assumptions 2 IV Discussion 2 V Summary 7 VI References 8 4 LIST OF FIGURES FIGURE 1. Single Line Diagram for Inverters SI AZ, SlB2, SlC2 & SlD2 9 2. Single Line Diagram for Inverter S1G 10 3. Single Line Diagram for Inverter SlN1 11 4. Single Line Diagram for Inverters SlGA &.S1GB 12 LIST DF ATTACHMENTS Attachment 1. Portions of DC Input Voltage Calculation Z-EDS-E0745 (9 sheets) 2. Inverters S1A2 to SlD2 Load Schedule (11 sheets) (Portions of Calc Z-EDS-E0523) 3. Inverter SIGA & SlGB Load Schedule (5 sheets) (Portions of Calc Z-EDS-E0629) 4. Portion of Drawing E-108 sheet 1 5. Inverter SINI Load Schedule (1 sheet) -i-i s 4= _-m_=__ m._:.E.m..=_a.m -.=_.liim c__J&xrr _- - m_ - _z_-r

a-l s. f I } Lt. INTRODUCTION . The purpose.ofJ this repor_t is _ to reevaluate the setpoints of sensing devices'ana timers associated with the. Class 1E and non-Class lE- -inverters at-the Rancho Seco Nuclear Generating ' Station. This responds toiNRC IE circular No. 79-02 which alerts to possible: undesirable. operation:of inverters aue:to improper settings.;~ This circular is also E called out in NRC'IE Bulletin 79-27swhich concerns. impact on plant safety due to loss of-120V AC buses. .II. - SCOPE _j 1 e l This report covers the: Class lE inverters Sl A2, 'S182, S1C2, SID2 and the f non-Class 1E inverters SlG, 51N1, SIGA and S1GB. The study investigates the impact of the following conditions on the operation of the inverters: .i - 1. Over and under voltage at the inverter DC input 2. Over and under voltage at the inverter AC output f ~1 3. Overload and short-circuit at the load busses IEC 79-02 requires the following to be considered as part of the review: 1. Determine whether or not _ time. delay _ circuitry'is used in the inverter units. If so,- have they been adjusted to the appropriate' set point as' required by equipment and the integrated system designs? g 2. Determine if the AC input voltage and transformer tap settings are ~ optimized to prevent. exceeding the inverter component nameplate ld maximum rated DC input voltage.in the event of a high AC input voltage transient. 3. If an alternate 120 volt source'is used in the design determine if the protection transfer circuitry of the inverter has been optimized within design limits'to ensure maximum possible availability of the inverter system during transient loading conaitions. An operating history of inexplicable transfers may De indicative of the above. .4. Determine if tne administrative controls employed by your facility ensures operability of safety systems af ter it's subcomponents (e.g., time delay relays, switches, etc.) have-been subjected to . maintenance or testing. 1-J 4 adk.m _ %i a.imme.ama.- _ m[_ .._._hm_-,_ .TE_-" _.h____ -__-.__m

n f III. ASSUMPTICHS 1. DC input voltage profile for inverters Sl A2, SIB 2, SlC2, S102, SlGA and SlGB are as provided in Calc Z-EDS-E0745, Attachment 1. 2. Setpoints for inverters S1 A2, SlB2, 51C2, 5102, S1GA and SlGB are as provided in E-10ll, sh.1628,1648,166B,1688 and 180A. i 3. The inverter loadings are as provided below: 3.1 - SlA2-S102: Calc Z-VBS-E0523 (Attachment 2) 3.2 SIG: E-108 sh.1 ( Attachaent 4) 3.3 SIN 1 : (Attachment 5) 3.4 SIGA & SlGB: Calc Z-EDS-E0629 (Attachment 3) 4. Tecnnical data are provided in the instruction manuals as follows: 4.1 S1 A2, S182, SlC2 & SID2 - E 8.02.1-11 4.2 SI G - E 8.01-46 4.3 SINI - E 8.02.2-4 4.4 SIGA & SIGB - E 8.02.1-18 5. The operation of the inverter during the last minute of the battery discharge cycle is not considered critical. Hence, the static l transfer switch may transfer to the bypass source at this point. IV. DISCUSSION 1. Class 1E Inverters Sl A2, SlB2, SIC 2 and S102. 1.1 The single line for the inverters $1 A2, SIB 2, $1C2 and $102 is shown in Fig. 1. The miniuum voltage during an emergency load cycle of the battery is given in Attachment 1. The inverter i load schedule is provided in Attachment 2. (Calc Z - VBS - E0523) The inverters are Elgar model 253-1-104 rated 105-140 VDC input and 120 V VAC nominal output at 208 A or 25 KVA.(Ref. ) 6) j 1.2 DC Input Undervoltage Sensor Setting j Shutdown Setting - 102 V DC for S1 A2 and S182 j 103 V 00 for SlC2 and SlD2 No time delay is provided prior to shutdown. From attachment 1, i the minimum voltage at the inverter exceeas 102 by an adequate margin for tolerance. When an undervoltage shutdown is received l the shutdown circuits described in section 1.4.2 operates. 1.3 AC Input Voltage and Transformer 'ap Settings. Rancho Seco does ) not have alternate inverter input which is not coupled to the l ba tte ry. Hence, the overvoltage concern from this alternate source does not apply. 1 : L - m___ - J C ~C7,i..iCm==m ^ ~ 3 E E G Ti~i l Z JJ G 1

s-e, c. 1.4 Transfer Switch 1.4. l ' 0/V-U/V Transfer Operating output voltage - 124 V AC 0/V Fast Transfer - 136 V DC (+10%) U/V Fast Transfer - 111 'V DC (-10%) U/V Slow Transfer - 118 VDC (-5%) By review of the inverter loading, Attachment 2, the largest single transient load is tnat of the battery room exhaust fan, at 2070 VA inrush. This load is small compared to the inverter capacity of 25 KVA and could not cause any undervoltage or overvoltage transient that will result.in a spurious transfer. 1.4.2 Overcurrent Shutdown / trip / transfer. Overcurrent shutdown - 344 A AC (165%) Overcurrent trip - 312A DC (150%) Trip Delay - 5 sec. There is no time delay operation on an overcurrent shutdown. The shutdown circuit is initiated by an output overcurrent or any of the fallowing conditions: DC input undervoltege Fuse open condition Low logic supply voltage The shutdown condition is held for at least 1/2 second before resta rt. The shutdown condition persists as long as the fault remains. Failure to clear the fault will eventually result in tripping the outpuc breaker CB2 after the five second trip delay. During an inverter shutdown the load is automatically transferred to the b,ypass source through the static transfer swi tch. From a review of the load schedule it is concluded that the-above current settings are much higher than any load inrush. Hence, spurious operation could not occur. l.5 Administrative controls. To ensure operability of the inverters, use is made of plant ) administrative procedures. Operation of the manual bypass switch and the manual operation of the static transfer switch is controllea via AP.4A, Safe Clearance Procedure Danger Tags. Testing and maintenance of inverter subcomponents is controlled ] via AP.48. Test Authorization Procedures. Maintenance procedure j is per EM 1768, Station Inverter Routine, Elgar Inverters. 1 l Operation of the inverters is covered by A.62,120 V AC Vital l System Operating Procedure. ) i l l ..} lL- .. -m

<s i i 2.0 Non-Class -lE Inverter SlG 2.1 The single line diagram for inverter SIG is shown on Fig 2 (Ref. l - Dwg. E106 Sh.11 ). The minimum voltage during an emergency load j cycle of, the battery is given in Attachment 1. The inverter i load schedule is given in Attachment 4 (Ref. Dwg. E108 Sh.1). J The inverter is Sclid State Products Inc. model i SPDCl 20-611 -120SS-60. It is rated 105-140 V DC input and 120 V i l AC-nominal output at 100 A or 12 K VA. (Ref. 7) '2.2 DC Input Undervoltage Sensor Setting i Shutdown Setting - 102. V DC Trip Setting - 100 V DC ho time delay is available prior to shutdown or trip. From Attachment I the DC input voltage exceeds 102 V DC for the entire load cycle by an adequate margin for tolerance. Hence, - no spurious shutdown could occur. 2.3 AC Input Voltage and Transformer Tap Setting i The one line diagram for the inverter input is similar to that - discussed in Section 1.3 above. Hence, as stated, no overvoltage condition could be imposed on the inverter due to voltage variations in tne 480 V system. 1 2.4 Transfer Switch 2.4.1 0/V - U/V Transfer Operating output voltage 120 V AC 0/V Fast Transfer - N/A U/V Fast Transfer - 108 V AC (-10%) Review of the inverter load schedule, Attachment-4, shows that the loads are associated with computer and radiation monitoring equipment. These loads are continuous. Hence, the above settings will not cause any spurious trans fers. 2.4.2 Overcurrent Shutdown / Transfer Overcurrent Shutdown - 150 A DC (150%) No time delays are provided prior to shutdown. On a shutdown overcurrent the output cycles on and off. The output circuit breaker is not tripped on a persistent a short-ci rcui t. On shutdown overcurrent, the transfer l switch transfers to the bypass source. From review of the load schedule it is concluded that the above overcurrent setting is much higher than any lead inrush. Hence spurious operatiois could not occur. q ! ~ ~ ~ ~~ -' e m N kW X CX:~M'M -^ 2_'j:f * ' - L' ) M ~W

h 4 . b 4 2.5 ' Amninistrative Controls These are similar to those in Section 1.5 except maintenance 4 f procedure is per EN 171 A, Station Inverter Routine, Static Products Inverter and operating instruction is per A.63,120 Volt Non-Vital System. 3.0 Non-Class 1E Inverter SIN 1 3.1 The single line diagram for inverter SIN 1 is shown on Fig 3 (Ref. Dwg E108 Sh.11 ). The minimum voltage during an emergency load cycle of the battery is given in. Attachment 1. The inverter load schedule is given in Attachment 5. The inverter is HDR Power System Inc. model STI-120-125-1. It is rated 105 - 140 V DC input and 120 V AC nomimal output at 208 A AC or 25 kVA. (Ref. 8) 3.2 DC Input Undervoltage Sensor Setting Shutdown Setting - None The undervoltage sensor is only used for alarm when the voltage is below the set point. No breaker trip or inverter shutdown is provided. 3 3.3 AC Input Voltage Transformer Tap Setting The one line diagram for the inverter inpu,t is similar to that discussed in Section 1.3 above. Hence, as stated, no overvoltage condition could be imposed on the inverter due to vcitage variations in the 480 V system. 3.4 Overcurrent Trip Overcurrent trip pickup - 312 A AC (150%) Overcurrent Trip Delay - 5 Sec. The output current sensor trips the output breaker CB2 when the current exceeds the trip setting af ter the preset time delay has elapsed. There is no transfer switch and bypass source for this inverter. From a review of the load schecule and considering a total load of only 60 A AC, it is concluded that the above overcurrent setting is much higher than any load inrush. Hence spurious operation could not occur..... N 4 w 6& @ W W ""'f" D6

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~ ~ l y, _g _t . y. ,m yue J3!5) Administrative Procedure Tnese a're similaroto those in Section~ 1:.5 except' maintenance il 4 procedure :is. per EM 171C SIN 1 Station ' Inverter' Routine and 'I ' operating ~ procedure;15. per A.63,120/V AC non-vital system. '4.0 Non-Class IE Inverter SIGA~& S1GB q j e 4.1 The single line diagram'for inverters SIGA 'and SIG8 is shown on i Figi4 -(Ref. _Dwg.: E108 Sh.11)., The minimum input voltage during: i the battery emergency cycle is given in Attachment'1. The-inverter. load schedul.e is given in' Attachment 3 (Calc j Z-EDS-E0629). The, inverter 1.is Elgar model 503-1-101. It is l . rated 105-140 V DC input and 120 V'. AC. nominal output at 417 A AC ll or 50 kVA. -(Ref. 9) 4.2; DC Iriput Undervoltage Sensor Sttting Shutdown Setting 103 V.DC No undervoltage shutdown delay is provided. From Attachment 1, the DC input voltage-to the inverter exceeds 103 V DC by an adequate _ margin for tolerance curing the entire load cycle. Hence, no. spurious shutdown could occur. In case of a shutdown undervoltage, the shutdown circuit discussed'in Section 4.4.2 will be initiated. 4.3 AC Input ' Voltage 'and Transformer Tap Settings The one line diagram for the inverter input is similar to that discussed in Section 1.3 above. ' Hence, as stated, no . overvoltage. condition could be imposed on the inverter due to voltage variations in the 480 V system.

4.4 Transfer Switch 4.4.1 0/V
U/V Transfer-Operating Output Voltage - 125 V AC O/V Fast Transfer - 137 V AC (+10%)

U/V Fast Transfer - 112 Y AC (-10%) U/V Slow Transfer - 119 V AC- (-5%) A review of the load. schedule, Attachment 6, shows that the largest single load is 4.32'kVA and all the loads are of the -continuous type. The largest loud is small in comparison with the full load _ rating of 50 kVA. The actual loads are 13.5 kVA for S1GA and 34.5 kVA for SIGO. Hence, the transfer setpoints will not be subject to spurious transfers. I 6-i l- .. =. = = 1 LL _.

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Shutdown / Trip / Transfer f Overcurrent Snutdown - 690. A - AC '(165%). ~ LTrip Current Pickup .625 A AC'(150%) Trip Time Delay'- 5 sec. i There is no time delay on an overcurrent shutdown. -The ~ C ishutdown' circuit isl initiated by.an output overcurrent, a 4 ' dc; input:undervoltage, fuse-open condition or low logic

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From'a - review of the load schedule 'it is ' concluded that + the. above.Overcurrent; setting exceeds any ' load inrush. Hence spurious operation can not. occur. At shutdown conoitions the output is shut for 1/2. second. On restart a high current limit will be. attained in order to try to clear the fault. Should the trip overcurrent levelLpersist for more than 5 seconds the output breaker'CB4 will be tripped. 4.5: Administrative Controls Same as-discussed Lin Section 1 ~ 5 except operating procedure is per. A.63,120 V Non-Vital system. V. ' Sununa ry - . As discussed under Section IV there are no' mechanisms for sp' conditions urious . operation of: the Class 1E and non Class lE inverters due to mentioned in 1ECf 79-02, with' settings provided in this report. "Specifically the following conclusions can be made:

1.. Tnere are no time delay circuitry. for the DC. input undervoltage trip or shutdown. The trip or shutdown settings have been properly chosen to prevent spurious operation.

2.- The concern over the AC input voltage and transformer tap settings that could cause internal inverter damage does not apply to the inverters at Rancho Seco. 3. The under and over-voltage transfer as well as the overcurrent settings have been optimized to prevent spurious operation. 4. Administrative procedures are in place to ensure availability of the inverters following repair or maintenance of an inverter cubcomponent. l l l L l t l i i i n" = _m = =. =

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.5. A.63,120 VL No'n-V_ ital iSystem. y p '6. Instruction _ Manual for Elgar modelf 253-1-104 Inverter,' E8.02.1 -11. - 7. ' Instruction Manual for. Solid State Model.SP0C-l'20-611.120SS-60 Inve rte r,.: E8.01 -46. Direct Current, i '8. Instruction ' Manual. for-HDR Power Sys Model STI-120-125-l ' Inverter, i .E8.02.2-4r j l 9. Instruction Manual for Elgar Model 503-1-101 Inverter, E8.02.1-18. .10. Direct Current System Design Basis'. Ill.; Vital Bus. System and.Non-Vital. Regulated 120 V AC System Design Basis. 12.: EM 171 A, Station Inverter ' Routine,. Static Products Inverters'.

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  • 'ON CALC. NO.

DATE 00 SI' N ~ Y$l*0*= & & AfSf $: O ~5' S 'Y E 05== 0 CHECKED SUBJECT $/6_, C/N/ 5/GA ad S/66 SHEET b OF 3 i 2,o /EFZPZtvCES 3 .c. A. HC8 Gd 985-l923, daftna lar 64nora$2/E66, kcommen a Urfc Laa' [(cro9e Clahons and s Sukkhbm 7 3,8, dalcalajOn a-Da-206oy 9 s.e. Ga/cahfiM & - ocs-rs ss <o 9 D. Cafeola/rdn 5 - 5AG-50629 <2 13 !.E Calcult&dn a - T'p3-gos23 18 & P. ealca.lahdn 2 - SPS-Eo09 3 se 36 Galeu.lahbn s - Dcs-C0& % ~ 18 3, H NEA/A Fl041, SleckIcCl hsip1 Grilttis 20 l i 21 22 23 j 22 25 26 27 28 29 30 31 1 32 1 33 j 34 33 1 *. __.__ SMUD 1420e 1484 _ _,,.,. ~.. - - - - n[ '. _.,;, wa_

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