ML17297B908

ESF Load Sequencer Software Verification & Validation Rept

ML17297B908
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Site:	Palo Verde
Issue date:	09/09/1982
From:	SIMPACT ASSOCIATES, INC.
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'

ESF LOAD SEQUENCER SOFTWARE VERIFICATION AND VALIDATION REPORT prepared by:

SIMPACT ASSOCIATES'NC.

5520 Ruffin Road San Diego, CA 92123 September 9,

1982

ESF LOAD SEQUENCER SOFTWARE VERIFICATION AND VALIDATION REPORT TABLE OF CONTENTS Pacae 1 ~

OBJECTIVE

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1 2.

STUDY PROCEDURE AND RESULTS

SUMMARY

3.

SPECIFICATION REQUIREMENTS

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4 4

SOFTWARE STRUCTURE

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5 5.

SYSTEM ROUTINES

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7 6.

UNDERVOLTAGE MONITORING 7.

ESF BUS LOAD SEQUENCING

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10 8.

AUTOTESTING...............................

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PERFORMANCE/DESIGN DEMONSTRATION TEST RESULTS 16 10.

CONCLUSION.......

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17 APPENDIX A

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ESF LOAD SEQUENCER SOFTWARE VERIFICATION AND VALIDATION REPORT 1

OBJECTIVE The objective of the Software Verification and Validation Study is to verify that the software of the ESF Load Sequencer meets the requirements of the design specification, and that no sneak software paths (circuits) exist that would render the system inoperable.

The ESF Load Sequencer is a

module in the Balance of Plant (BOP)

Engineered Safety Features Actuation System (ESFAS) supplied by General Atomic Company (GA) to the Palo Verde Nuclear Generating Station under Arizona Public Service Company Purchase Order 10407-13-JM-104 and Bechtel Power Corporation Speci fication 13-JM-104.

This module controls loading of the station ESF bus and diesel generators under loss of power conditions or if an accident signal is present.

The purpose of this report is to outline the methods used to perform this study and to detail the findings of the study.

2.

STUDY PROCEDURE AND RESULTS

SUMMARY

The following steps were taken to per form the study:

a

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Review of Bechtel Specification (13-JM-104).

This specification was reviewed in detail to determine the functional requirements of the ESF Load Sequencer.

b.

Review of General Atomic Operations and Maintenance Manual (E-115-760).

This manual was reviewed to determine how the functional requirements had been implemented and in particular, which functions had been implemented in software.

The major functions implemented in software are:

Monitoring of accident signals and sequencing control of ESF bus loads.

Monitoring loss of power condition and generation of load shed signal and loss of power off delay.

iii. Auto-testing of all ESFAS Modules including ESF Load Sequence r.

c ~

d.

Review of Software Documentation (SK-1678).

This documentation includes program listings and flowcharts for all software modules in the ESF Load Sequencer.

The documentation was reviewed for completeness.

In

addition,

" each module was reviewed individually to determine that the flowcharts matched the program

code, that the program code was properly documented and that the code as implemented performed the required functions.

Review of Performance Test Report (E-115-787) and Design Demonstration Test Report (E-160-972).

The Performance Test demonstrates the functional performance of the ESFAS equipment.

The Design Demonstration Test verifies that the design of the ESF Load Sequencer permits no credible common failure modes to exist in response to credible input perturbations and series of events.

Both test reports were reviewed to determine whether the tests exercised all program paths within the software of the ESF Load Sequencer.

The results of this study show that the software of the ESF Load Sequencer meets the requirements of ESFAS Specification, 13-JM-104.

Two minor anomalies were noted in the so ftware, neither of which will cause a

malfunction of the ESFAS equipment.

The first anomaly results from disabling interrupts during test of the bottom half of RAM memory.

This causes an increase in the sampling interval of the contact debounce algorithm which in turn delays posting of an input change.

Since the delay is of the order of l0

msec, there is no significant affect on the performance of the ESFAS system.

P The second anomaly is in the load sequencer logic and ~.can cause 2

msec pulses on certain relay outputs.

The duration of these pulses is not sufficient to cause activation of any dev ice.

3 ~

SPECIFICATION REQUIREMENTS The Bechtel Specification, 13-JM-104, defines the technical requirements for all aspects of the ESFAS system.

The functions specific to the ESF Load Sequencer are defined in Section 4.5.14 of that specification.

These functions are implemented in the ESF Load Sequencer software.

In addition, this software also controls the auto-testing functions"', as specified in Section 4.5.13 and certain alarm contact outputs as specified in Section 4.5.16.

The major 'requirements of the specification are:

a.

Monitor undervoltage input from LOP/LS module.

Upon detection of undervoltage condition generate a

1 second load shed pulse and activate loss of power signal.

When undervoltage condition clears ensure that it remains in the cleared condition for 60 seconds before deactivating loss of power signal.

b.

Monitor loss of power and accident signals.

Upon detection of specific combinations of these

inputs, initiate one of four loading sequences or modes (see specification attachment 4-1, sheet

8).

Activate one contact per sequencer mode to indicate automatic sequencing in progress.

Activate up to ten independent, time separated loading signals, adjustable in one second increments over a total time span of 60 seconds (for sequencer outputs and

timing, see speci fication attachment 4-2, tables 8

and 9, respectively) c.

Automatically test the operation of the maximum possible portion of the ESFAS system.

Upon detection of circuit malfunction, immediately initiate remote annunciator and indicate malfunction locally.

This automatic

testing, under normal or failure condition of the test features must not interfere with the normal operation of system or cause protective action.

4 SOFTWARE STRUCTURE The software consists of a

number of routines which operate in conjunction with each other to fulfill all functions of the system.

These routines fall into four categories.

a.

System Routines.

These routines handle timer interrupts and input/output.

They also control the execution of the other programs in the system.

F b.

c Task Routines.

These routines implement the major functions in the system, i.e.,

under voltage monitoring, mode detection/output sequencing and auto-testing.

Task Subroutines.

These routines implement specific functions within the task routines.

d.

Common Sub routines These routines impl em ent func tions common to several tasks.

The software structure and hierarchy is shown in Figure 4-1.

Appendix A contains a profile of each routine in the system.

The profile lists the following information for each routine:

a.

Category (e.g.,

system routine, task, etc.)

b.

Function c.

Verification Study Data, including:

accuracy and completeness of flowcharts accuracy and completeness of program listing comments illo specific design demonstration/performance tests which exercise the code 1v ~

v ~

coding or design errors detected in the routine comments

c SEVE 1:

57&769

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~LOP QA'CK szrs cd rsrZ umnm 7STA/

These common subroutines called by multiple tasks or task subroutines Figure 4-1 Software Structure Chart

5 ~

SYSTEM ROUTINES To meet the functional requirements defined in section 3, the system must provide the following major features:

a.

Accurate time base generator to control time-related functions e.g.,

input debouncing, load shed pulse duration, loss-of-power off delay and sequencing of loads onto the ESF bus.

b.

Concurrent operation of several different functions e.g.,

undervol tag e monitoring, mode determination/load sequencing and automatic testing.

These features are implemented in two system

routines, the timer interrupt handler (RST75/RST65) and the executive program (EXEC).

The overall design of these programs was validated and the detailed implementation of each feature was verified.

Particular emphasis was placed on verification of the major features outlined above.

The system meets the time base generator requirements by implementation of two timer interrupts.

The lower priority interrupt occurs every 2 msec, the higher priority interrupt occurs every 10 msec.

The 2 msec interrupt routine reads all digital inputs and processes them through a debounce routine.

The debounce algorithm is based on the 2 msec sampling time and ensures that the input has reached a steady state before reporting any change to the other software routines.

The 10 msec interrupt routine sets a software flag for the executive program in addition to debouncing the inputs.

The executive uses this 10 msec flag to allocate execution time to each of

.the concurrent functions and as a

time base to schedule programs handling time-related functions.

The executive allocates 10 msec time slots for execution of the concurrent functions required in the system.

Each concurrent function outlined in (b) above is designed as a

separate program(s)

(see Table 5-1).

These

programs, or

tasks, run under 'control of the executive which allocates 10 msec time slots to each as required.

Within the 10 msec time slot the task must execute to completion and return control to the executive.

The system complies with this requi'rement; the execution time for each task is shown in Table 5-1.

Every 250 msec the executive allocates one 10 msec time slot to the task SO which monitors the undervoltage condition and checks for a stall condition in the opposite train (redundant system). It also allocates one 10 msec time slot to the task Sl which detects changes in the sequencer mode and performs the bus load sequencing operation.

The remaining twenty-three 10 msec time slots are allocated to autotesting tasks.

The sequential time slot during which each task may be executed is shown in Table 5-1.

Since the task SO and Sl

TABZ.E 5-1 Task

tame Function Performed SO Check loss of power condition

• Generate/check stall opposite train signal Executed dur ing time-slot Approx imate execution time I

1 msec Sl Sequencer mode determination Sequencer output control 3 msec S2

• Generate 10msec/50msec module test pul se 1 msec S7 S24

• Check 50 msec module test pulse on

• Check 50 msec module test pulse off TlRAM

• Test top hal f of RAM memory

,, BlRAM

• Test bottom hal f of RAM memory ROM

• Test ROM memory S3

• Check 10 msec module test pulse on S4

• Check 10 msec module test pulse off 24 2-24 2-24 2-24 1 msec 1 msec 1 msec 1 msec 7 msec 8 msec 4 msec Auto testing functions are executed every 25th time slot, they execute at 250 msec (1/4 sec) intervals.

This synchronous execution permits the timed execution of functions at 1 sec intervals as required for load shed

pulse, loss-of-power off delay and sequencing of loads onto the ESF bus.

This inherent program timing is also used in the autotesting software to control the duration of test pulses to the other ESF modules.

The design was found to be valid and met the system requirements of the specification.

No discrepancies were detected in the software implementation of the design.

6.

UNDERVOLTAGE MONITORING The design specification defines the following major requirements for the undervoltage monitoring function:

a.

Monitor an input from LOP/LS module for undervoltage condition on the 4.16 kV ESF bus.

b.

Upon occurrence of undervoltage condition, generate ajone second load shed pulse and set loss of power condition.

c.

If undervoltage condition clears and remains cleared for 60 sec, clear loss of power condition (off-delay).

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These functions are implemented in subroutine CKLOP which is executed every 250 msec by the task SO.

The overall design of the subroutine was validated and the detailed implementation of each feature was verified.

Particular emphasis was placed on verification of the major features outlined above.

II The program monitors the bus undervoltage input from the LOP/LS module.

Upon detection of an undervoltage condition it activates the load shed output to the LOP/LS module and illuminates the loss of power indicator on the Load Sequencer module.

Internally it indicates the loss of power condition by setting a software flag.

The program uses the synchronous nature of the task 'it executes every 250 msec) to control the duration of the load shed pulse.

On the fourth execution of the program after the signal is activated, it is deactivated terminating the load shed pulse.

After generation of the load shed pulse, the system continues to monitor the undervoltage input.

If the undervoltage clears and remains in the cleared state for 60 seconds, the loss of power indicator is extinguished and the loss of power software flag is cleared.

Again, the synchronous nature of the task is used to determine this 60 sec off-delay.

Should the undervoltage condition re-occur within the 60 sec off-delay period, the design of the software ensures that the 60 sec off-delay is terminated without resetting the loss of power indicator or flag.

A new 60 sec off-delay is started when the undervoltage clears again.

The design of the software also ensures that the load shed pulse occurs only once for each loss of power condition.

The load shed pulse is generated when the undervoltage condition is first d etec ted.

No further load shed pul'ses are gener ated until the 60 sec off-delay completes although several undervoltage conditions may occur within this time interval.

The design was found to be valid and met the undervoltage monitoring requirement of the specification.

No discrepancies were detected in the software implementation of the design.

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7 ESF BUS LOAD SEQUENC ING The design specification defines the following major requirements for the ESF bus load sequencing function:

a.

Monitor loss of power condition and accident signal inputs for specified combinations of these inputs.

b.

Upon detection of initi ate/terminate load combinations which cause spec ification attachment I

any such combinatxon, sequencing mode.

The input mode transitions are defined in 4-1, sheet 8.

c.

Upon initiation of any mode, - start bus loading sequence defined for that mode per specification attachment 4-2, table 9.

Initiate contact closure to indicate currently active mode..

d.

Sequence loads onto ESF bus at the specified time intervals for the active mode.

,y W

e.

Upon termination of a sequencing mode, return all outputs to idle state (mode 0) and clear mode indication contact.

The mode determination function is implemented in task Sl which executes every 2SO msec.

The load sequencing function is implemented in the subroutine OSEQ.

OSEQ is called by task Sl when the sequencer is in any mode other than mode 0.

The overall design of these programs was validated and the detailed implementation of each feature was verified.

Particular emphasis was placed on verification of the major features outlined above.

The task Sl checks initially for an active sequencing mode (modes 1-4).

If such a

mode is active, it verifies that the specified inputs are still in the required state.

All inputs which are not specified for the mode are considered as "don' care" inputs and are ignored.

If all specif ied inputs are still true, no mode change is required.

If some inputs have changed

state, the sequencer returns to the idle state (mode 0),

the mode indication output is cleared and all sequencer output signals are returned to the mode 0

condition.

The sequencer always returns to the idle state when conditions for the active sequencing mode are no longer true even though conditions may be correct for entry into another sequencing mode.

The next execution of the task will cause the transition to the new mode.

If the sequencer is in the idle state (mode 0) upon entry to the

task, the loss of power software flag and the accident signals are checked.

If the state of these inputs matches the state specified for any of the sequencing modes 1-4, that mode is activated.

Again, all inputs which are not specified for the mode are treated as "don' care" conditions.

Upon transition to the mode, the mode indication output is set and the sequencing timer is started.

Prior to exiting task Sl, a check of the current sequencing mode is made.

If the mode is not zero (output. sequence active) the subroutine OSEQ is called.

This routine handles the contact closure outputs and the time activation of these signals necessary to sequence the loads onto the ESF gus.

Since the routine executes every 1/4 sec the time resolution is sufficiently accurate to meet the load sequencing requirements.

The routine is table-driven in design; this means that all sequencing modes are handled by the same executable program code with variable parameters (e.g.,

output

signal, activation time) -stored in a

table of each mode.

All table entries were verified and found to be correct.

A design anomaly was found in the routine OSEQ.

As with all d igital outputs in the

system, this routine sets/cl ears outputs in the output bit map.

This output bit map is copied to the output ports every 2

msec by the timer interrupt routine.

Certain actuation signals exist which change state twice during a

sequencing mode e.g.,

Charging Pumps in mode 2.

These require two entries in the mode table which specifies the parameters for

OSEQ, one to activate the

output, the other to deactivate the output.

The design of the software is such that if, for

example, the signal is activated at time 0 sec and deactivated at time 40 sec, every time the routine executes after the 40 sec

time, the signal will first be set, then cleared in the output bit map.

If an interrupt occurs while the bit is set, the bit is copied from the bit map to the output port.

The bit will. remain set until the next interrupt, 2,msec later, by which time OSEQ will have reset the bit.

The probability of occurrence of this 2 msec pulse is small; in addition, the duration of the pulse is insufficient to cause actuation of the controlled dev'ice.

This anomaly will cause no malfunction of the ESFAS system.

f All other features of the design were found to be valid and met the requirements of the specification.

No discrepancies were detected in the software implementation of the design.

AUTOTESTING a.

Test automatically and continually maximum possible portion of the ESFAS system.

b.

Under normal or failure conditions of the testing syst: em, ensure that it interferes in no way with the normal operation of the system.

Upon detection of circuit malfunction, initiate a remote annunciator and locally indicate malfunction.

interruption of autotesting at any Co d.

Permit convenient time.

The design specification defines the following requirements for the autotesting function:

Theqe functions are implemented in three categories; redundant system (opposite train) monitoring by task SO, ESFAS module testing by tasks S2, S3, S4, S7 and

S24, and Load Sequencer testing by tasks

TlRAM, BlRAM and ROM.

The overall design of each test was validated and the detailed implementation of the testing features verified.

The task SO monitors a

square wave input with a

10 second period which is generated by the opposite train (redundant system).

If a transition is not detected every 5 secs, an indicator on the Load Sequencer module is illuminated to indicate a stall.

In addition, the stall opposite train annunciator is activated.

The task SO also generates a

square wave output with a 10 second period which is monitored by the opposite train.

This feature continually monitors the correct operation of each system.

The

. other testing features are executed only if the Manual/Auto switch is in the Auto posi<ion and only if the sequencer is in the idle state (mode

0).

The executive routine monitors the Manual/Auto switch and prevents scheduling of the autotest tasks if it is in the Manual position.

This meets the requirement to permit convenient interruption of autotesting at any time.

The system tests the other modules within the ESFAS system by generation of test pulses to those modules.

The tasks S2, S3 and S4 working in conjunction with each other, generate and test responses to 10 msec test pulses.

The tasks S2, S7 and S24 generate and test responses to 50 msec test pulses.

The synchronous nature of task scheduling by the executive, permits generation of accurate pulse lengths.

This test pulse software is table driven in the same manner as the output sequencer (OSEQ) routine.'he test

output, the expected module input and the expected test return are all defined within the parameter table for each module.

To test a module the output is set.

At 10 msec (or 50 msec) later the state of the module inputs and the test return inputs are tested.

If found in the correct state the test output is cleared.

At 10 msec (or 170 msec) later the state of the module inputs and the test return inputs are again tested to ensure that they have returned to the cleared state.

It should be noted that the program not only tests the correct response of the module input and test return which correspond to the activated test

output, but

. it also tests all other module inputs and test returns to ensure that they do "not respond.

If an error is detected the test is terminated and the test indicator lamp on the module under test is flashed.

The autotest suspend annunciator is also activated.

These features satisfy the requirements specified in item (c) above.

Under normal autotesting conditions the task SO checks for the presence of a

real

input, as opposed to a test output response.

If a real input is found, autotesting is suspended and initiation of the new sequencer mode (if required) wi3.1 be performed by task Sl.

Suspension of autotesting due to a

real input or due to a module test failure, does not affect the mode determination or the load sequencing functions of the Load Sequence r in any way.

Autotesting of the Load Sequencer module itself is performed by the tasks

T1RAM, B1RAM and ROM.

These tasks test the top half of RAN memory, the bottom half of RAN memory and ROM

memory, respectively.

The RAM memory tests do a

write/read/compare operation of all data patterns into all RAM memory locations.

The ROM memory test does a

checksum calculation/comparison operation on all RON memory locations.

If an error is detected in any of these tests, an error light pattern is flashed on the Load Sequencer module and all software functions are inhibited.

It is not possible to continue system operation when

'an error is detected in one of the tests as failure of RAN or ROM can cause unpredictable operation of the system.

An anomaly was found in the design of task BlRAM.

Inputs are sampled by the interrupt routine which normally executes at 2

msec intervals.

Any input change is processed by a debounce algorithm which requires three consecutive sample values to determine the true debounced state.

This results in a delay of up to 4

msec between the occurrence of the change and the reporting of it to the processing task.

Interrupts are disab3.ed while testing the bottom half of RAM.

This ensures that no data is changed during execution of the test which requires slightly in excess of 8

msec of the 10 msec exection slot assigned by the Executive.

The inputs are sampled once prior to disabling of the interrupt, once upon reenabling of the interrupt and a third time at the end of the 10 ms execution time slot (see Figure 8-1).

Assuming this extended sample interval (8

msec) will still match the mechanical

. characteristics of the input contact, the delay between the occurrence of the change and the reporting of it to the processing task (i.e.,

time required for three consecutive samples of the input) has now increased to 10 msec.

This is an increase of 150%

in the reporting delay experienced with the 2 msec sample interval.

It will have no significant affect on the operation of the Load Sequencer however; the undervoltage monitoring and sequencer mode determination functions are only performed once every" 250 msec.

All other features of the design were found to be valid and met the requirements of the specification.

No discrepancies were detected in the software implementation of the design.

77/'IF (fGEc.)

ExECvVON Ssor hf Imper sRHPuNc'~7'M ExE<O77eu Figure 8-1 Input sampling timing diagram

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9 PERFORMANCE/DESIGN DEMONSTRATION TEST RESULTS The resul ts of the Per formance Test Report (E-115-787) and the Design Demonstration Test Report (E-160-972) were reviewed to determine whether all program paths within the software had been exercised by these tests.

Appendix A lists tests which exercised the logic of each program.

In general, almost-all program paths were tested.

Exceptions are the failure paths for the RAM and ROM test

programs, and 'he fatal error routine (HALT) to which they transfer control.

These program paths are straightforward and perform their designed function.

Al1 test results indicate that the design and implementation of the software fulfill the requirements of the design speci fication.

10.

CONC LUS ION The results of this study show that the software of the ESF Load Sequencer meets all the requirements of the ESFAS Design Specification 13-JM-104.

In addition, no sneak circuits or software paths exist that would render the system inoperable.

The two anomalies which were

noted, 2

msec pulses on sequencer output relays and variations in debounce timinp of inputs, will cause no malfunction in the ESFAS equipment.

APPENDIX A PROGRAM DATA

Prog ram Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

HALT System Routine Term ina tes system ex ec ution on fa tal error.

Displays flashing error code in lights of Load Sequencer module."

Complete and correct Adequa te This routine was not exercised by either the Design Demonstration Test or the Per formance Test.

Design/Coding Er ro rs:

Comments:

None None

Program Name:

Ca tegory:

COLD System Routine Func tx on.

Flowchart:

Sour ce Cod e Comments:

Exercised by:

Design/Coding Errors:

Comments:

Initializes so ftware and hardware on system power up (cold start).

Complete and correct Adequate Performance Test on start up (ELA 342-0062, Sheet 33 of 70)

None None A-2

Program Name:

Category:

Function:

RST75/RST65 System Routine Processes timer interrupts.

Reads inputs and stores debounced results in input bit map.

Copies output bitimap to output ports.

Sets 10 msec interrupt flag fo r executive.

Flowchart:

Source Code Comments:

Exercised by:

Com pletc and co rrec t Adequate Per formance Test and Design Demonstration Test on each interrupt (every 2 msec).

Design/Cod ing Errors:

Comments:

None None A-3

Program Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

Des ig n/Cod ing Er rors:

Comments:

DEBNC System Routine Debounces dig ital inputs.

Called by system routine RST75/RST65.

Com pl e te and Co rrec t Adequa te Performance Test and Design Test on each interrupt (every 2 msec).

None None

Prog ram Name:

Category:

INIT System Routine Function:

Flowchart:

Source Code Comments:

Exercised by:

Initializes I/O ports and timers.

Called by system routine COLD.

Complete and co rr ec t Adequate performance Test on start up (ELA 342-0062 Sheet 33 of 70)

Design/Cod ing Errors:

Comments:

None None

Proq ram Name:

Category:

Function:

F15wchart:

So ur ce Cod e Comments:

Ex ere ised by:

Design/Coding Errors:

Comments:

EXEC System Routine Complete and correct Adequate

~ $

Autotest section of Performance Test (ELA 342-0062 Sheet 55 of 70).

None None Controls execution of tasks within system.

A-6

Program Name:

Category:

Function:

SO Task Calls STALL to check for stall of opposite train (redundant system).,

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P, Updates system running flag for this train.

Calls CKLOP to monitor undervoltage condition..

Checks for any real inputs to stop/resume autotesting Flowchart:

I Source Code Comments:

Complete and correct Ad equa te Exercised by:

Stall/system running; tested by Performance Test (ELA 342-0062, Sheet 65 of 70).

Undervol tag e monitoring; tested by De,sign Demonstration Test (ELA 342-0063, Page l6 of 43, Test l)

Stop autotesting on real input; tested by Design Demonstration Test (ELA 342-0063, Page 22 of 43, Test 6)

Resume autotesting on absence of real inputs tested by Design Demonstration Test (ELA 342 0063, Page 24/43, Test SA/SB)

Design/Cod ing Errors:

Comments:

None None A-7

Prog ram Name:

Category:

Function:

Task Monitors loss of power and accident signals to determine sequencing

mode, P,

Calls output sequencing (OSEQ) routine to sequence'us loads.

Flowchart:

So ur ce Cod e Comments:

Exercised by:

Complete and correct.

Accurate Mode transitions tested by Desing Demonstration Test (ELA 342-0063, Pages 22 and 23 of 43, Tests 6,

7A and 79).

Design/Cod ing Errors:

Comments:

None None A-8

Program Name:

Category:

Function:

S2 Task Activates test pul se for mod ul e autotesting.

Flowchart:

Source Code Comments:

Exercised by:

Complete and correct Adequa te Per fo rmance Test (EI.A 342-0062, Sheet 58 of 70).

Des ign/Cod ing Er ro rs:

Comments:

None None A-9

Program Name:

Category:

Function:

S3 Task Checks "on" condition of test return for 10 msec test pulse (module auto testing) and deactivate test pulse.

Flowchart:

Source Code Comments:

Exercised by:

Complete and correct Adequa te per fo rmance Test (ELA 343-0062, Sheet 58 of 70).

Design/Coding Er rors:

Comments:

None 1

Task, S3, S4, S7 and S24 are all a

part of the same source code module (TEST) and use a

common error exit, TSTERR.

A-1 0

Prog ram Name:

Ca tegory:

Function:

S4 Task Check "off" condition of test return for 10 msec test pulse (module autotesting)

Flowchart:

Source Code Comments:

Exercised by:

Complete and corret Adequa te Performance Test (ELA 34-0062, Sheet 58 of 70).

Design/Coding Errors:

Comments:

None Part of source code module TEST.

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Program Name:

Category:

Function:

S7 Task Checks "on" condition of test return for 50 msec test pulse (module auto testing) and deactivate hest pul se.

Flowchart:

Source Code Comments:

Exercised by:

Complete and'orrect Ad equa te Per formance Test

.(ELA 342-0062, Shweet 58 of 70).

Des ign/Cod ing Er ro rs:

Comments:

None part of source code module TEST.

A-l2

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Program Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

S24 Task Checks "off" condition of test return for 50 msec test pulse (module autotesting)

Com pl e te and co rrec t Adequa te Per fo rmance Test (ELA 342-0062, Sheet 58 of 70).

Design/Coding Er ro rs; Comments:

None Part of source code module 'TEST.

Program Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

TlRAM Task Tests the top half of RAM memory.

Compl etc and co rrec t.

Adequa te Autotest section of Per formance Test (ELA 342-0062, Sheet 58 of

70).

Fail ur e cond ition not encountered during

test, hence no testing of failure path.

Design/Coding Errors:

Comments:

None None A-l4

Program Name:

Category:

Function:

Flowchart:

So ur c e Cod e Comments:

Exercised by:

B1RAM Task Tests the bottom hal f of RAM memory.

Complete and correct Adequa te Autotest section of Per formance Test (EM 642-0062, Sheet 58 of

70).

Failure condition not encountered during test hence no testing of failure path.

Design/Cod ing Errors:

This test disables interrupt for approximately 8

msec.

This affects the input debouncing algorithm and can delay updating of debounced inputs in input bit map.

No coding errors.

Comments:

None A-1 5

Program Name:

Category:

Function:

Flowchart:

So ur ce Cod e Comments:

Exercised by; ROM Task Tests ROM memory Complete and correct Ad equa te Autotest section of Performance Test (ELA 642-0062, Sheet 58 of

70).

Fa ilur e condition not encountered during test hence no testing of failure path.

Design/Cod ing Er rors:

Comments:

None None A-l6

Program Name:

Category:

Function:

Flowchart:

So ur ce Cod e Comments:

Exercised by:

Design/Coding Errors:

Comments:

STALL Task Subroutine called by SO Check for stall of opposite train (redundant system)

Complete and correct Adequa te Exercised continuously during testing.

Stall condition simulated dur ing Per formance Test

~ (ELA 342-0062<

Sheet 65/70)

None None A-17

C Program Name:

Category:

Function:

Flowe ha rt:

So ur ce Code Comments:

Exercised by:

Des ign/Cod ing Er ro rs:

Comments:

LIGHT Task Subroutine called by SO Toggles lights which have blink status set.

f p

Complete and Co rrec t Minimal Per formance Test failure simulation.

(ELA 342-0062, Sheet 64 of 70).

None None A-1 8

Program Name:

Category:

Function:

CKLOP Task Subroutine called by SO Monitors undervol tage condition and generates load shed pulse and loss of power ind ication.

Flowchart:

Source Code Comments:

Exercised by:

Desig/Coding Errors:

Comments:

Complete and correct Adequa te All paths exercised by Design Demonstration Test (ELA 342-0063, Page 19 of 43, Test 4

and Page 18 of 43, Test

3).

None None A-1 9

Program Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

OSEQ Task Subroutine called by Sl Controls time sequencing of loads onto ESF bus.

Complete and correct Ad equa te Actuation response time measurements o f Per fo rmance Test (ELA 342-0062, Sheet 40 of 70 to. Sheet 44 of 70).

Design/Coding Errors:

Design can cause unwanted 2

msec pulses on signals which change state twice during bus loading sequence.

Comments None A-20

Program Name:

Category:

Function:

Flowchart:

Source Code Comments:

Exercised by:

ITT1/ITT2 Task Subroutine called by 82 Initializes parameters for 10msec/50msec pulse testing of module Complete and correct Adequa te Autotest section of Performance Test (ELA 342-0062, Sheet 58 of 70).

Design/Code Errors:

Comments:

None Flowcharts for these programs are included with programs for task S2.

A-21

C

'L Frog r am name:

Category:

Function:

Flowchar t:

Source Code Comments:

Exercised by:

Design/Coding Errors:

Comments:

ONC K Task Subroutine called by S3 and S7.

Checks "on" condition for spec ified input, "off" condition for all other inputs.

p Complete and correct Adequate Autotest section of Per formance Test (ELA 342-0062, Sheet 58 of 70).

None None A-22

~

~

~

4

\\

Program Name:

Category:

OFFCK Task Subroutine called by S4 and S24 Function:

Flowchart:

Source Code Comments:

Exercised by:

Check "off" condition for specified input.

Complete and correc t Adequa te Autotest section of Per formance Test (ELA342-0062, Sheet 58 f 70).

Design/Coding Errors:

Comments:

None None A-23

Program Name:

Category:

Function:

Flowchart:

So ur ce Cod e Commen ts:

Exercised by:

NEXT Task Subroutine called by S2 and S24 Advances testing to next entry in parameter table used for 10msec/50msec pul se testing.

Complete and correct Adequa te Autotest section of Per formance Test (ELA 342-0062

< Sheet 58 of 70).

Design/Coding Errors:

Comments:

None None

Program Name:

Category:

Function:

Flowchart:

UPDATE Common Subroutine Updates test parameters for 10msec/50msec pulse test of module, Complete and correct Source Code Comments:

Ad equa te Exercised by:

Autotest gee tion of Per formance Test (ELA 3432-0062, Sheet 58 of 70).

Des ig n/Cod ing Er ro rs:

Comments:

None None A-25

Program Name:

Ca tegory:

Function:

Flowchart:

TS TW Common Sub ro utine Compares byte (8 bits) with specified byte of input bit map.

~

4 Complete and correct So ur ce Code Comments:

Exercised by:

Minimal Autotestinq section of Per formance Test (ELA 342-0062, Sheet 58 of 70).

Design/Coding Errors:

Comments:

None None A-26

Program Name:

Category:

Function:

SETB Common Subroutine Sets bit corresponding to designated output in output bit map.

Flowchart:

So ur ce Code Comments:

Exercised by:

Design/Coding Errors:

Comments:

Complete and correct Minimal Load shed

-pulse generation of Design

'emonstration Test (ELA 342-0062, Page 19 of 43, Test

4).

None None A-27

Program Name:

Ca tegory:

Function:

Flowchart:

So ur ce Cod e Commen ts:

Exerc ised by:

Des ign/Cod ing Er ro rs:

Comm en ts:

CLRB Common Subroutine Clears bit corresponding to designated output in output bit map.

Complete and correct Ninimal Load Shed pulse generation of Design Demonstration Test (ELA 342-0062, Page 19 of 43, Test

4).

None None A-28

~

~ I Program Name:

Category:

TSTB Common Subroutine Function:

Flowchart:

Source Code Comments:

Exercised by:

Design/Coding Errors:

Comments:

Tests bit corresponding to designated input in input bit map.

Complete and correct Minimal Load Shed, pulse generation of Design Demonstration Test (ELA 342-0062, Page l9 of 43, Test

4).

4 None None A-29

~

~

Prog ram Name:

Category:

Function:

SUSP Common Subroutine Calls STOP to terminate sequenc ing mode or autotesting, then sets system in autotesting suspended state.

Flowchart:

Source Code Comments Exercised by:

Design/Cod ing Er ro rs:

Comments:

Complete and correct Adequa te Autotest term ination in Design Demonstration Test (ELA 342-0063, Page 24 of 43, Test SA/8B).

None None A-30

Program Name:

Category:

Function:

STOP Common Subroutine Terminates sequencing mode or autotesting Sets all outputs to idle state and turns off all lights except STOP.

Flowchart:

So ur c e Cod e Comm en ts:

Exercised by:

Complete and correct Ad equa te Mode l or mode 4 termination in Design Demonstration Test (ELA 342-0063, Page 24 of 43, Test SA/SB).

Design/Coding Errors:

Comments:

None None A-3l

, r I

BOP ESFAS CHANGE Scope of Work The following software modules have been changed to redefine the bit 7 of OBM+3 from the mode 9 indicator to the stall opposite train annunciator:

By searching the cross reference files for OBM+3 and A7:

1.

EQUATE.SRC:

Change 1 place for the redefinition of bit 7.

2.

S1

.SRC:

Remove code in 2 places where the mode 5 indicator was both set and reset.

3.

STALL.SRC:

Add code in 2 places to both set and reset the stall opposite train annunciator.

4.

SUBS

.SRC:

Change code in STOP routine such that it will not set the mode 9 indicator bit.

5 ~

In addition, add a date and revision module.

(ID.SRC)

Link this module last so that it will be in the second EPROM.

Put the following ASCII data in the date and revision module:

DATE August 18, 1982 REVISION PVLS.03

t...

~ Van

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RMS, 60 HZ potential for 60 seconds without degradation of isolation...".

The procedure outlined below and performed once every 13.3 years during the plant life for the isolator assembly should verify the voltage isolation characteristic of the cross-train isolator assembly (0342-7100). Because the isolator assembly, is partitioned into two sections via the common input and output return lines (designed to minimize the number of terminals needed on the terminal blocks for circuit interface), two tests will be required to be performed on each assembly. The first test will verify isolator circuits 1 through 8 and 10 (see schematic 0342-7110), while the second test will check out isolator circuits 9 and ll through 18. If a failure is detected in either test, common troubleshooting techniques may need to be used to locate the failed individual isolators within the applicable group. This additional trouble locating effort is forced by the common input return and output return printed circuit layout. Figure 1 conceptually indicates the test approach and equipment setup for the voltage isolation standoff verification test. As a first step, the 0342-7100 isolator assembly must be removed from the applicable logic cabinet by carefully disconnecting the associated input and output wiring harness. Particular attention should be given to disturbing the lead dress as little as possible so as to minimize wiring reconnection errors.

Secondly, a shorting jumper should be placed across each protection diode associated with both the input and output of each optical-coupler device.

This jumper protects against damage to either the input led or the output transistor of the isolator from high capacitive charging currents impressed by high dv/dt's during the application of the test voltage. Thirdly, a high voltage breakdown generator (GAC recommends the standard "AC Hypot Junior" unit manufactured by Associated

Research, Inc.,

8221 North Kimball Avenue, Skokie, Illinois, 60076, or equivalent.) is impressed across terminals TB1-9 and TB2-1, and checks are made for any 'reakdown with the test generator set to 1500 V RES, 60 HZ output. This test voltage should be applied for 60 seconds minimum. The test generator must then be moved between terminals TB1-20 and TB2-12 and the same isolation breakdown check made. l After successful bench test completion, the test jumpers should be removed, the isolation assembly carefully re-installed in the logic cabinet, and wiring connection verified. After verification,'normal manual test pro-cedures should be conducted to verify that each cross train isolator circuit employed functions properly. TYPICAL MGIC HDPOL6 t'KlVirg

SIGNAL,

+15v LMOTTDtl:2 RE%DUE /50LA1VRA.SSEME{Y P-ROM IOrnlE. C4BNJET'DJ2. 7ESC TYF'(CA L ISOLATOtZ QlR.CUIT'~ <<>&~ SHDRl IhJ&

JUMPER, oPFosIM logic TR'4ul Eau>F'waHT O'PASCAL opPosn E THaN RECeIVirin C<V'zGV C,Sv ZXX C79 oc 7BI (A)950 2

l I Rl Ca,l I ~@ Y (20)" Qg U/ 5'u>5A OP7V-iSOLA7VAf R3 Q~~2 3 /i54 I I I I I I 0<') %0>) ~ CR2 RYI '/ig+ ~ g2 %Fly To P.e, PCS'tM4M 4N46 sc-4 Cs 1,c LCICAMS (MF'o~ SHORTIMG JUMPER VIELGCTRfC "HYPOT" Terna. 'Igloo VReSC~> 60Ez. Pi'du&E / XTP5T I COVE'gS lSOtATOR C<RCUl7S l mROu&HS;(O Pv HYFoT TE~~~ PFGlhl& COhlhlBC':Xh BETSlKChL TE:RHlu~& TBl-Q e~O TB2-l-Isolator network schematic ~~ + UU 22S I+ 4 +~ 2 For IN-sITU Bypot testing to I( T<rtoesQ lg'>9 << HYPN TESll62. insure 1500 VAC isolation standoff characteristic. THI-20 4-~b TM~ l2. HI1'r.HDB/',21 7C 9 April 1979 DISCRETE SEl/iI CO.')DUCTORS OPTO-ELECTPONI C DEYICES 2,2.10 Opto-electi onic SPECI FI CATION MIL-S-19500 NIL-S-19500 None AlT~A<&n A A'~<+/9 /'HW: u'rial'~Pz~~ Au~~r~nows Semiconductor

9evices, Group X.

DESCRIPTION Light Emitting Diode (LED) Opto-el ectroni c Coupler (Isolator) LED Alpha-numeric Display ~~~rzoH, The part failure rate model, )p, is: / b "C ~E "0 failures/10 hours ~ (O.NH)(I.S)(>)F00) = O.&l2FaI~ZeS/<~C ~~~ cCdZ &0CH +n/gag where: >b = base failure rate in failures/10 hrs., Table 2.2.10-4. mC = complexity factor, Table 2.2.10-3. environmental factor, Table 2.2.10-1. >~ = quality factor, Table 2.2.10-2. The above nedel;includes li"ht from the liaht emit+ina concerning light degradation, TABLE 2.2.10-1 >E,. ENVIRONS NTAL FACTOR 5GF PP Z"ri4 ~ t@aasrrrom all failures exce t deoradation of output d dgi see Bibl',ography item No. 49. TABLE 2.2.10-2 >q, EQUALITY FACTOR Environment ~G SF G A.T AIF N G) NU AUT liF M Ql 1 2 2. 8. 10 Assv&r&Q ~pl/Ac Q~BABIIcr~ 6 Folic vs. WnZ EACH c/S~ INC%7M. CIRCuiT AAlb CSeiCC RrWQruCX'e ma, EACii i>S~ CSCCWv. /c/iJn rAm Ourpur &RCVC7" 7M 7DTAI ISOMER A4ic.v~ dATG Is: A =g 4/,. = /g /o. biz)~~c 'ou~' ~rotc OR ]g PITB/= = /), = //C.7/Begs = /9.Byes guality Level JANTXV JANTX JAN 10 LQIER* 50 +10 PLAAT~+*

• -A lies to a

i nern:eti pp packaged alpha-numeric displays and to NON-JA.') hermetic packaged LED's and isolators.

• "-Applies tc all devic s

encapsulated ws-.K organic materials.. 2.2.10-1 OCV~RKul-TRA<Sveg. ETIO O'Cra'), eaIaV &N&rl-aO7FVT lIIDAMAM A.PJK'R Bo,DDo Icec///Is (GE os) c~~~ M<cIAc, P'4zi 4 ~ DEFT c~M>tc S'H pDaAEQT RKlhBIL/7Y3 %IS M>I+<I~C jest < APPLICAAK z~ec.ovep cuir~.~ 'rW PVII65~ MfAS Eh'rIPM~, I'5 IAI57C~l~uy ~A~ IGO49797~ ~AuJ ul~i~io&EV?..r D ~ C TABLE 2.2.10-3 +C> COMPLEXITY FACTOR MfL-HDBK-217C 9 April 1979 DISCRETE SEMICONDUCTORS OPTO-ELECTRONIC DEVICES Device Device Single L'ED 1.0 Al ha-Numeric Dis la s* Q ~'in le Isolators ~Sim le~* " w/1 trans. " w/2 trans. " w/lin. amp. " w/lin. amp. 1 trans. " w/lin. amp. & 2 trans. Dual Isolators Simple** " w/2 trans. " w/4 trans. " w/2 lin. amps. " w/2 lin. amps. & 2 trans. " w/2 lin. amps. & 4 trans. 1 5 ~l:8 2.2 3.3 3.6 4.0 2.3 2.7 3.3 5.0 5.4 6.0 1 character 1 character w/logic chip 2 character 2 character w/logic chip 3 character 3 character w/logic chi p 4 character 5 character 6 character 7 character 8 character 9 character 10 character 2.8 3.8 4.0 5.0 4.9 5.9 5.7 6.3 6.9 7.4 8.0 8.5 8.9 +-The number of characters in a display is the number of characters contained in a sinole sealed package. For

example, a

4 character disap ay comprising 4 separatel packaged single characters mounted together wou d oe .4-one character displays, not 1-four character display. ~*-Simple isolator(s) contains only a lignt-emitting element(s) and a light detecting element(s). 2.2.10-2 HzL HDBv 217C pri 1 1979 DISCRETE SEMI Col)DUCTORS OPTO ELECTRONIC DEVICES TABLE 2.2.10-4 OPTO-ELECTRONIC SEt"iICONDUCTOR DEVICE BASE FAILURE RATE, Xb, It/ FAILURES PER 10 HOURS ( op~ max op~ max) T (OC) .1 .2 .3 .4 .5'6 .7 .8 .9 10 0 5 10 15 20 .0002 .0002 .0003 .0004 .0005 .0003 .OOO4 .0005 .0006 .0008 .0005 .0006 .0008 .0010 .0012 .0008 .0010 .0012 .0014 .0017 .OO12 .OO17 .OO24 .0014 .0020 .0028 .0017 .0024 .0034 .0020 .0028 -.0040 .0024 .0034 .0048 .0034 .0040 .0048 .0058 .0071 .0048 .0071 .0058 .0088 .0071 .0112 .0088 .0146 .0112 .0200 25 30 35 40 45 .0006 .0008 .0010 .0012 .0014 .0010 .001 2 .0014 .0017 .0020 .0014 . 0017 .0020 .0024 .0028 .0020 .0024 .0028 .0034 .0040 .0028 .0040 .0058 .0034 .0048 .0071 .0040 .0058 .0088 .0048 .0071 .0112 .0058 .0088 .0146 .0088 .0146 .0288 .0112 .0200 .0146 .0288 .0200 .0288 50 ~ 55 6r. 6~ 70 .0017 .0024 ~ VM to .0034 .0048 .0034 .0040 .0048 .0058 .0071 .0048 .0058 .0071 .0088 . 0112 .0071 .0112 .0200 .0088 .0146 .0288 .0112 .0200 .0146 .0288 .0200 75 '" 80 85 90 95 .0040 .0048 .0058 .0071 .0088 .0058 .0071 .0088 .0112 .0146 .0088 . 0112 .0146 .0200 .0208 .0146 .0288 .0200 .0288 100 105 llO 115 .0112 .0200 .0146 .0288 .0200 .0288

• -Ifderating information for isolators and displays is unavailable, assume S=.5, TS=25oC, and:

Tmax = 125 C for hermetic isolators. Tmax = 100 C for plastic isol'ators and for all displays. See Section 2.2.11.2(7) 5 (9) for correction factor for S ratio and for the appropriate value of T to use with above table. 2.2.10-3 33. 35. 36. 37. 38. 39. 4O. 41. MlL-HDBK-21 7C 9 April 1979 >Nichrome Resistor Properties and Reliability", RADC-TR-73-181, A 765534. "Dormancy 5 Power On-Off Cycling Effects on Electronic Equipment 5 Part Reliability", RADC-TR-73-248, AD 768519. "Use of Marranties for Defense Avionic Equipment", RADC-TR-73<<249, AD 769399/7. "Reliability Acquisition Costs", RADC-TR-73-334, AD 916286L. "Electrical Characterization of Complex Microcircuits", RADC-TR-73-373, AD 775740. "Reliability Study of Polyimide/Glass Multilayer Boards", RADC-TR-73-400, AD 77194. "Infrared Testing of Multilayer Boards", RADC-TR-74-88, AD 780550. "Laser Reliability Prediction",'ADC-TR-75-210, AD A016437. "Reliability Model for M'.niature Blower Motors Per MIL-B-23071B", RADC-TR-75-178, AD A013735. 42., "Reliability Investigation of the MSC 2010 Transistors", ECOM-0092-F-72, AD B000815L. 43. 44. 46. 47. "Reliability Investigations of the MSC 1330A and MSC 13308 Microwave Power Trans i s tors", AD 923318L. 'RCA TA8694 and TA8777 Microwave Power Transistor Reliability Investigation", AD A007587. "Reliability Prediction for Microwave Transistors", RADC-TR 313, AD A003643. "Reliability Study of Microwave Power Transistors, RADC-TR-75-18, AD A007788. "PAD". Nonelectronic Reliability Notebook, Revised", RADC-TR-75-22, AD A005657. ~49. 50. "Reliability/Design: Thermal Applications", MIL-HDBK-251, 19 January 1978. "Development of Failure Rate Heels for Semiconductor Optoelectroric Devices", FAA-RD-76-134, AD A( 29163. "High Power Micro~ave Tube Reliability Study", FAA-RD-76-172, AD A033612. C-3 NIL-HDBK;217C 9 April 1979 'ISCRETE SEMI CONDUCTORS I>(+ X) = maximum rated zener current at TS G.F.. stress correction factor per (8) below (4) Group YII Microwave Mixer Diodes Operating Spike Leakage (ergs) S = Rated Burnout Energy at 25 degrees C. (5) Group YII Microwave Detector Diodes POp (Operating Power Dissipation) P+,X (Rated Power at 25 degrees C.) (6) Group VIII Yaractor, Step Recover, and Tunnel Diodes. S OP (C.F.} PmX where: POP = actual power dissipated PMAX = maximum rated power at TS C.F. = stress correction factor per (8) below (7) Group X Opto-electronic Semiconductor Devices. S -"OP (C.F.) IMAX ~~ (47S) =,> ~87+ 8(I} where: or S = OP (C.F.} PWaX IQP operating average forward current I+,X = maximum rated ave age forward current at TS POP ~ actual power dissi pated P~X = maximum rated po~er at TS C.F. ~ stress correction factor per (9) below. 2.2.11-5 Nli.-HDBK-217C 9 'Apri 1 1979 'DISCRETE SEMICONDUCTORS ~ 'I (8)tress Correction Factor Devices. a. Devices with TS = 25 200 degrees C. (C.F. ) and temperature corrections for Silicon degrees C 8 TX = 175 degrees C to C.F. = 1 b. Devices with TS >25 degrees C E, TX = 175 degrees C to 200 degrees C. C.F. 175 - TS 150 c. Devices with C.F. = MAX 150 TS = 25 degrees C 8 T~X <175 degrees C. - 25 and enter Ab table with T = TA r T=TC+ d. Devices with TS )25 degrees C MAX) 8 T~X <175'degrees C. CF;~ MAX S 150 and enter Ab table with T = TA + (175 - TNX) or T = TC + (175 - T~X) (9) '.'..': '.-.;"; - Factor (C.F.) and temperature correction for Opto-electronic Oevices. .'or devices with TS > 25 C. or T~AX < 125oC., or both, C..F. = MAX S 100 !00-25 0.75 IOO and enter Xb table with T = TA + (125 - TX) =35+ Cl25-IM3~ 60 or T = TC (125 -T~X) 2.2.11-6 ~ ~ ~ HIL-HDBK-21 7C 9 April 1979 DISCRETE SEMICONDUCTORS 2.2'll INSTRUCTIONS FOR USE OF SEMICONDUCTOR MODELS 2.2.11.1 Device Ratings Transistors are normally rated at maximum power dissipation and diodes at maximum current permissible. Usually each device is.given two temperature rating points: 1 TMAX - Maximum permissible junction temperature. 2 TS - Maximum ambient or case temperature at which 100 percent of the rated load can be dissipated without causing the specified maximum junction temperature to be exceeded. (Case temperatures are given primarily for power devices used on heat sinks.) As the ambient or case temperature rises above the TS value, the inter~: 'emperature rise (i.e., the power load) must be decreased so T~X is no+ exceeded. This is illustrated in Figure 2.2.11-1. 9 ~ +1 > 100 CY D taJF 50 CL I CC O CO b4t O. a. 0 I I l 1 I I Maximum Use Rating A C MAX FIGURE 2.2.11-1. Conventional Derating Curve Note: T = temperature at which deratinq begins TMA = maximum rated junction temperature MAX TA = ambient temperature TC = case temperature Q MIL-HDBK-217C 9 April 1979 only to have the equipment production procedures damage the parts or introduce latent defects. Total equipment program descriptions as they might vary with different part quality mixes is beyond the scope of this Handbook. Reliability managoment and quality control procedures are described in other DOD standards and publications. Nevertheless, when a proposed equipment development is pushing the state-of-the-art and has a high reliability. requirement necessitating high quality parts, the total equipment program should be given careful scrutiny and not gust ttte parts quaIity. Otherwise, the low failure rates as predicted by the models for high quality parts will not be valid. c. Use Environment. All part reliability models include the effects of environmental stresses through the factor, irE. The definitions of these environments are shown in Table 2-3. The T;E factor is quantified within each part failure rate model. These environm nts encompass the major areas of equipment use. Some equipment may experience'ore than one environment during its normal use,

e. g., equipment in spacecraft.

In such a case, the reliability analysis should be segmented, namely, missile launch (ML) conditions during boost and return from orbit, and space flight (SF) while in orbit. TABLE 2-3 ENVIROtNENTAL SYMBOL IDENT IF I CATION AND DESCRIPTION EtlVIROltHEWT

Ground, Benign

Space, Flight

Ground, Fixed Ground, Mobile SYtSOL GB SF NOtsI lAL E sVIROi4HsENTAL CO tDITIOt S Nearlv zero environmental stress with optimum engineerinq operation and maintenance.

Earth orbital. Approaches

Ground, Benign conditions without access for maintenance.

Vehicle neither under powered flight nor in atmospheric re-entry. Conditions less than ideal to include install-ation in permanent racks with adequate cool-ing air, maintenance by military personnel and possible installation in unheated buildings. Conditions more severe than those for GF, mostly for vibration and shock. Cooling air supply may also be more limited, and maintenance less uniform. 2~3 <i r )4,<< 217C ri 1 1979 ~,-.,il"O:<t)EN3

g,gl, "cl<ered I

Un- ,~qttered %E SYtlBOL NOtlINAL EWVIROt)MENTAL CONDITIONS Surface ship condition" similar to GF but subject to occasional high shock and vibrat i on. Nominal surface shipborne conditions but with repetitive high levels of shock and vibration.

Airborne, Inhabited, Transport

Airborne, Inhabited Fighter

Airborne, Uninhabited, Transport AIF Typical conditions in transport or bomber compartments occupied by aircrew without environmental extremes of pressure, temperature, shock and vibration, and installed on long mission aircraft such as transports and bombers.

Same as AIT but'installed on high performance aircraft such as fighters and intercepters. Bomb bay, equipment bay, tail, or wing installations where extreme pressure, vibration, and temperature cycling may be aggravated by contamination from oil, hydraulic fluid and engine exhaust. Installed on long mission aircraft such as transports and bombers.

Airborne, Uninhabited, Fighter

Missile, Launch AUF ML Same as A

but installed on high performanN aircraft such as fighters and intercepters. Severe conditions of noise, vibration, and other environments related to missile launch, and space vehi cl e boost into orbit, vehi cl e re-entry an'd landing by parachute. Conditions may also apply to installation near main rocket engines during launch operations. d. Part Failure Rate Models. Par t failure rate models for microelectronic parts are significantly different form those for other parts and are presented entirely in Section 2.1. Another type of model is used on most other parts; a <yp>cal example is the following one for discrete semiconductors: 2-4 MUD STATE III GEM ERAL ELECTR lC I i t r ~ ~ 1 ~ I 'e I r stfJ'vAjMXthcvd 3." -A~' 't(I:< Wu Wl 'ur( JP

p l~(a I

~ v r +vs~ rvuhr Lop 4+ evoe v ~ + S ~ ~ ~ e' r FEATURES: ~ Fast switching speeds ~ High DC current transfer ratio ~ High isolation resistance ~ 2500 volts isolation voltage ~ I/O compatible with integrated circuits fIndicates JEDEC tc istcrcd values ~V t 1 I I I t I s~L J photon CoUpfed Isolator 4Ã38-4N38A Ga As Infrared Emitting Diode 8'PN Silicon Photo-Transistor The General Electric 4N38 and 4N38A consist of a gallium'rsenide infrared emitting diode coupled with a silicon photo~ transistor in a dual in-line package. J P'q I J J 'Stdnn ~l. I c+ ~sr(ee vsnuets[1 Vj~V $ )os IS ~ I ~ uo ~ S $ 00 nto Idt ~ CI I $ ~ 4 ~ 4 ~ s4l Ot ~ 04 $ 0 tC ~ CD QeOi OI s Os 0'$0. ~ ~ t t0 0$ 00 ~ 0 ~t'0$ s IC t 'IS l ~ 4 $0$ IOC tS ~ ~ Se OI4 $ ~ I S IS ,ICS AS tSI tto I~I I II I Se ~ I It reCstt I see I Iwles ~Ivvvvu eveeeun se svv ves ve 'oeeu vsse verruca osreevur se ~s rar I' t Ierrue osevenleoueveere $ 0 seals esroee ~ 4 Ines ~ uevv~ ve roue Vnu ve eav Vous ~Ierr rvseo absolute maximum ratings: (25'C) (unless otherwise specified) tStorage Temperature -55 to 150 C. Operating Temperature -55 to 100 C. Lead Soldering Time (at 260 C) 10 seconds. 0150 milliwatts 80 milliamps 3 ampere INFRARED EMITTING DIODE tPower Dissipation t Forward Current (Continuous) tForward Current (Peak) (Pulse width 300psec,2%duty cycle) t Reverse Voltage 3 volts QDcsatc 2.0mW/OCabove 2SQCambicnt. PHOTO TRANSISTOR, fPower Dissipation 00150 milliwatts tVcEO 80 volts tVcao 80 volts tVEco 7 volts Collector Current (Continuous) 100 mllliamps 0'Dcratc 2.0 mw/ C above 25 Cambicnt. fTotal device dissipation 8 TA o 25 C. PD 250 mK fDctatc 3.3 mW/ Cabove 25 Cambicnt. individual electrical characteristics (25'C) INFRARED EMITTING DIODE fForward Voltage (IF 10m A) t Reverse Current (VR ~ 3V) Capacitance V~0,f ~ 1 MHz 1.2 1.5 100 50 TYP. MAX. UNITS volts microamps picofarads PHOTO.TRANSISTOR tBreakdown Voltage V<SR>cEo (IC = ImA, IF = 0) tBreakdown Voltage V<SR) CEO (Ic = I/IA IF 0) fBreakdown Voltage V<SR>ECO (IE ~ I OOPA, IF = 0) tCollector Dark Current lcEO (VcE 60V, IF O) tCollector Dark Current lcao (VcE ~ 60V, IF ~O) MIN. 7YP. 80 80 MAX. 50 20 UNITS volts volts volts nanoamps nanoamps coupled electrical characteristics (25'C)

s. ut ron t~olra e 60Hz with the input lerraioals (diode(

shooed tonelher and the oulput terra(nels (transistor) shor Ied Ioget her. 4N38'A 4N38A MIN. TYP. 1500 1775 MAX. UNITS volts (peak) vo ts tpea volts R!htS sc t Saturation oltagc o ector mitter F = mA, C = mA Resistance IRED to Photo. Transistor (C" 500 volts) Capacitance IRED to Photo-Transistor (t<'0 volts, f= I hfHz) DC Current Transfer Ration (IF $$ 10mA, VcE 10V) Switching Speeds (VCE = lOV, IC, ~ 2mA, RI. ~ IOOQ) Turnn TimC ton Turnff Time tetrf 127 10 100 1 1.0 volts gigaohms picofarad jO microseconds mtcroseconds ~ q ~ TYPlCAL CHARACTERISTlCS I? c IP Lo O.I O? O IJ H NORMALIZEO To: VCE ~ lo VOLTS Tp ~ lomA I qq q ~ I.o O ~sq ~4 ?I O qq H NORMALIZED To: Vgg ~ lo VOLTS Js lorn A TA ~ +2S'C IP q 20mA IS ~ IomA JP ~ 5mA O.OII 2 1 6 6 lo 20 Ao 60 60 loo Zp INPUT CURRENT mA

1. OUTPUT CURRENT VS INPUT CURRENT l5

+25 +65 TA AMBIENT TEMPERATURE C

2. OUTPUT CURRENT VS TEMPERATURE

+IOC Io lp ~ SomA q I 6 I? IJ 5 Ioo al .OI I cc I.o cI O O.l co? Obt M q NORMALIZEO To: Vgg ~ lo VOLTS IP ~ lomA Ip ~ lomA I p ~ Sm Dol l.o I.S Vr FORWARO VOLTAGE VOLTS

3. INPUT CHARACTERISTICS 2.0 0.01

.OI .I I Io IOC Vgg COLLECTOR To EMITTER VOLTAGE VOLTS

4. OUTPUT CHARACTERISTICS Io

~? e> 5"e> 0 IOI E c O" IO' Vcg ~ 60V NORMALIZEO To: vqq 60 Yqqqq TP ~ 0 TA ~ ~25qC Boo ~ 250 I? ~ 200 m ISO cOI II So qq ~ q Vgg ~ IOV IP ~ 5mA VGA ~ IOV Ip ~ qomA Vqg ~ IOV Is ~ 50mA e2 +2S 050 ITS +IOO +I25 TA AMBIENT TEMPERATURE iC

6. NORMALIZEDDARK CURRENT VS TEMPERATURE iSO 25 0

+25 +$0 +VS +IOC TA AMBIENT TEMPERATURE qC

6. COLLECTOR BASE CURRENT VS TEMPERATURE

Optical Couple/Isolators Transistor Output olation Volta e is 7500 V Min eve es. See notes. Couplers are designed to provide isolation protection fromhigh-voltage transients, surge voltage, or low-level noise that would otherwise damage the input or gen-erate erroneous information. They allow interfacing systems of different logic levels, different grounds. etc., that would otherwise be incompatible. ~Mti~rl.t cou lers are tested and s ecified to an isolati n v Ita Motorola offers a wide array of standard devices with a wide range of specifications (including the firstseries of DIP transistors and Darlington couplers to achieve JEDEC registration: transistors - 4N25 thru 4N38, and Darlingtons 4N29 thru 4N33). AlfMotorola couplers are Ul Recognized with File Number E54915. CASE 73DA The Transl ~tor Coupler is probably the most popular form of isolator since it offers moderate speec (8"craximateiy 300 kHz), sensitivity and economy, In addition, the collector-base junc-tion can be used as a photodiode to achieve higher speeds. The output in the diode mode is lower, requiring amplification for more usable output levels. Device Type TIL112 TIL115 IL15 MCT26 TIL111 TIL114 IL12 MOC1006 4N27 ,4N28 H11A4 TIL124 TIL153 IL74 MOC1005 TIL125 TIL154 4N25 4N26 H11A2 H11A3 H11A520 ILl MCT2 TIL116. 4N3 HIIAS MCT271 H11A1 H11A550 TIL117 TIL126 TIL155 CNY17 MCT275 MCT272 MCT277 4N35 4N36 4N37 H11A5100 MCT273 MCT274 DC Currant Trisnafer Ratio sys Min 2.0 2.0 6.0 6.0 8.0 8.0 10 10 10 10 10 10 10 12.5 20 20 20 20 20 20 20 20 20 20 20 20 30 45 50 50 50 50 50 62 70 75 100 100 100 100 100 125 225 V(BA)CEO Volts Min 20 20 30 30 30 30 20 30 30 30 30 30 30 20 30 30 30 30 30 30 30 30 30 30 30 80 30 30 30 30 30 30 30 70 80 30 30 30 30 30 30 30 30 Darlington Output tsolation Voltage is 7500 V (Min) on all devices. See notes. The Dartlngton Transistor Coupler is used when high transfer ratios and increased output current capability are needed. The speed. appioximateiy 30 kHz, is slower than the transistor type but the transfer ratio can be as much as ten tiines as high as the single transistor type. Device Type 4N31 H1183 4N29 4N30 MCA230 H'I18255 MCA255 H11B2 MCA231 MOC119'IL119'IL113 MOC8030'IL127 TIL128'IL156 TIL157'1181 4N32 4N33 MOC8020'OC8050'OC8021'C Current Transfer Ratio % Min 50 100 100 100 100 100 100 200 200 300 300 300 300 300 300 300 300 500 500 SOO 500 500 \\000 V(BR)CEO Volts Min 30 25 30 30 30 55 55 25 30 30 30 30 80 30 30 30 30 25 30 30 50 80 50 s nn csea is el ~ ~:

l. Isolshonsuioevonsoe.viso,s

~ sninieinslaemceaieirc tnc bsessaown rshno For inis irsi LEO pins s ena 2 es commonena phoioliensisloi pins ~.5,ena6siecommon

2. Ail Moiosoie coo pins are specihea

~i 1500 Veo peen i seconasi snis ususay eaeeeai inc onainslas ~ s peCihce hon ena Jforc sr i@rica rs>urs By: W.H. Sahrn Technical Contributors: J. Cook R. Finke A. Fox R. Grandys M. Tarzia LayoutiDesign: D. Barney Production: R. Brewster D. Kay B. Dillon-fUlalone N. Patrick S"-;";IlGOf'OUCTOA Pf(".DU"TS OEPARTMElfi B. RELIABILITYPREDICTION OF CIRCUITS CONTAINING IRED's Previously the IRED phenomena of light output decrease, as the time current flows through it, was mentioned. This presents a dilemma to the circuit designer attempting to provide adequate margins for bias values unless he can predict what minimum value of light output, from the IRED, he can expect at the end of thc design life of his equipment. Based on the results of tests performed at G.E. and at customer's facilities (who were kind enough to furnish us test data and summaries) the G.E. Application Engineering Center has developed design guidelines to allow the prediction of the approximate worst case, end of life, IRED performance. The basis of the predic-tion is the observed behavior of the ratio of light output after operation to the initial value of light output. It also is based on the observation that all devices do not behave identically in this ratio in time, but that a distribution with identifiabl tenth, fiftieth (median) and ninetieth percentile points exists at any time the ratio is calculated. Use of this tenth percentile ratio (90~e of the devices are better than this) and the distribution of licht out ut (or CTR for courl rs abovo the specified minimum value allows the product of specllle mtnlmum light output and tenth percentile ratio, predicted at end of life, to be used as a reasonable approximation of minimum

SUMMARY

OF TESTS USED TO OBTAIN !RED DESIGN GUIDE LINES lpS 3mA 5mA 40mA 20mA 25 C 2Q 1000 Hr. 3mA 20 1000 Hr. I 5mA 16 1000 Hr. I 10mA 27 500, 1000 Hr. I 5, 10. 20mA 40 C 55 C 70 C 80 C 108 1000 Hr. 10mA 100 C 25mA 50mA 60mA 75mA 100mA 20 1500 Hr. 10mA 20 1000 Hr. I 5.10.20.60mA 79 IK, 15K, 30K EIr.

l. 10.

I OOrnA 2Q 20 1500 Hr. 1500 Hr 10mA 10mA 20 1500 Hr. 10mA 60 1500 Hr. 10mA 40 15QO Hr. 10mA )0 1500 Hr. 10mA 163 1000, 3000, 5000 Hr. 10mA 90 168, 1500 Hr.

1. 10. 100mA This chart tepresents about 2.0 million device bouts of opetation on 625 dual in line optocouplets and t l l hecmetic IstED's.

FORMAT OF DATA PRESENTATION: SAMPLE SlZE TEST DURATION lpM CURRENT

O. end of life value. Although this does not rcprcsent the worst possible case, no correlation can bo found between initial light output and rate of decrease in light output, and so the percentage of devices expected to be less than thc guideline derived number approaches zero. These guidelines, as can be noted, are based on fair sample sizes, although both larger samples than these and greater precision, higher resolution, measurements could provide better fits. To make the guideline dev-elopment less obscure, the discussion will trace the steps followed in defining these design guide-lines and, in the process, develop the guidelines. IVIIen the percent of initial value of light output (or current transfer ratio in couplers) of an IRED on an operating life test, is plotted against the time the IRED has been operated, two phenomena become apparent. The long-term behavior is found to be a straight line when the ratio is plotted on a logarithmic time scale. The short-term behavior is found to have a much shallower slope, on the same plot, than thc long-term behavior. This effect is illustrated by the fact that the long-term straight line can be extrapolated back towards zero and will usually inter-sect the initial value line at a time between 10 and 100 hours. TlIese properties combine to allow the response to be described>y a "virtual initial time" and the slope of the linc passing through that time point. This had been recognized in other work. The problems with predicting response are the variety of test conditions at which both stress and measurement data have been taken, and the spread of data at the readout points. It was recognized that the fail in light output was accelerated by either stressing the IRED harder, i.e., at a higher current (IFs) and/or temperature, or by monitoring the test results at lower current (IFM) levels. Precise acceleration factors have yet to be determined due to lot-to-lot variability. Fortunately, circuit design purposes can be served by a less precise model, which only attempts to serve the requirements of circuit desi n. For this approach, as mentioned before, we pay attention to the lower decile of the distribution a'nd its change in time. I EU ~ IIO cf E IOO K IR ~~ 90 2 80 O I 70 K ~ 60 I w 50 CC LP Io L le!. goop song BEST FIT STRAIGHT I LINE LOWER DECILE I LONG TERM RESPONSE long HIIA P~ I 300 mw, Irg

• 60mA, 1 p~ ~ lomA TWO LOTS, 36 UNITS, 180,000 DEY. HRS.

VIRTUAL IOO - IOOO INITIAI. STRESS TIME - HOURS IOOOO LIFE TEST RESULTS ILLUSTRATINGOBSERVED CHANGE IN IRFO OUTPUT VNITKOPERATING TlhlE 41

The question naturally arises of the applicability of this description to time periods beyond the one and five thousand hourtimes that the majority of the tests stopped at. Fortunately, tests have been completed on discrete IRED's for 30 000 hours. test d e othin unex ected'a ens at extrem I ion times as can . This is reinforcing evidei.ce indicating the superiority of the G.E. silicon doped, liquid phase epitaxially grown IRED. grown IRED. llo 100 90 PERCENTILE I-90 ~ eo O g TO I~ 60 50 u 40 ';I~ 50 20 10 Io PERCENTILE 50 PERCENTILE DISCRETE XRED TEST CONDITIONS Iq ~ IOO mA Tc

• 25'C l4 DEVICES IO io'o~

TIME IN HOURS LONG TERM IRED LIFE TEST RESULTS IO' iO'0 YRS io'lotting the response (best straight line) of various test conditions on a single graph, the acceleration due to raising stress current (IFs) is e sily seen. Higher temperatures during stress cause tile same effect, and can be accomplislied by raising the ambient or by self-heating (in a coupler by dissipating power in the output device). Lowering the current at wliich the IRED light output is monitored, (IFsl) also accelerates the phenomena, but in lookii.g at many test results, it appears that the ratio of IFS /IFM iS t!ie key facto." affecting the slope besides temperature. 42

O, 100 eC W CL CL'C W) 4.cn~ 2 eC ~CI 90 CCi I ZZ W4J CL. O ~W IC:4I 80 OIL DUAL INLINE COUPLERS TEST CONDITIONS Irg ~ 60mA Tg ~ 25~C IO DEVICES " '80mA 'Om1 ~ ~ ~ ~ IO 100 IOOO STRESS TIME - HOURS EFFECT OF MEASUREMENT CURRENT ON SI.OPE O I I-IOO eC W CL D W> 4cn~ 2 eC ~I 90 I I-22 WW CL O ~w 80 Pp CL DUAL INLINE COUPLERS T E ST COND IT ION9 Ira 25mA Ir4 > IOmA 20 DEVICES PER STRESS 7srIICSC c 25, 10eC 55eC 700 ICO IOOO STRESS TIME - HOURS EFFECT OF STRESS TEMPERATURE ON SLOPE O I IOO ~CW CL eC 4I0

4. g l/I~

cI= 90 CLZ 22 WW CCO ~w 80 Pp CL DUAL INLINE COUPLERS TEST CONDITIONS Ir~ IOmA Tq ~ 25'C Pout we ~ 300 mW 36 AND 15 DEVICES PER TEST ~r 20m 60~ IOO IOOO STRESS TIME-HOURS EFFECT OF STRESS CURRENT ON SLOPE ~ ~ ~ey, ~... ~ ~eeeeeeee met~~ ee ~ ~ ~ ' 'ee~ ~ o~ e t~ ' eeeee ~

~ When the temperature effect is plotted as an acceleration vs. temperature, a fair straight line fit is found, as illustrated below. This temperature acceleration factor represents the ratios of the slopes of the lower decile lines of various temperature stresses. The fit is not perfect, but is good enough to be useful. It contains both discrete IRED data (LED55 series) and optocoupler data (Hl 1 series) and appears to fit both equally. With this, and the determination of the coupled thermal resistance in the optocoupler (i.e., the heating factor for the IRED from power dissipated in the output device), it was attempted to fit the IFs/IFM ratio into the model. After many attempts to find models which fit various phenomena better, and the generation of additional data to try to fill holes, it was decided that two factors contributed to the inability of defining a tight fit single line. These are lot-to-lot and sampling variability and the precision (and volume) of data required to find the slope at low I Fs/ IEM ratios and low temperatures. These factors cause the best model found to enclose a band of observed values, as can be seen. 20 lu 9-rLH + I I5 0~ 4l O.~W own 4 rc g ~@ g lo su no nw Q rc cc ru 9 g I-O > ~ O. o I rc ru ru rL' rc 2 0 IO trs/IFII STRESS TO MONITOR IREO FORWARD CURRENT RATIO IOO 20 30 40 50 . 60 70 80 90 IOO OPERATING TEMPERATURE - 'C Blas Currant Effect Temperature Effect IREO OUTPUT VS. TIME SLOPE PREDICTION CURVES ASSUMINQ A VIRTUALINITIALTIME OF 50 HOURS To use this data the circuit designer must define a desired lifetime, the degree of control he has on minimum and maximum values of IF in any single socket, and the temperature environ-ment to which the circuit is exposed. A simple example of the design procedure illustrates its use. Assume the need for an 4N35 which will provide 10mA of output current at 5 Volts VCE after 100,000 hours of 55'C opera-tion. To find the IRED current needed to provide this, we need tile minir'num specified CTR of the 4N35, the estimated slope of the lower decile of light output vs. time and the teinperature acceleration of that slope at 55'C. The 4N35 specification indicates a rninimuin CTR of 100~~o, that for IE values of up to 20 mA the CTR is relatively constant and that at 55'C the CTR willbe about 0.85 times its 25'C value ( /. The center of the range of slopes vs. IFs/IFM is con- /6 CTRL <T servatively chosen at a ratio of 1.3 and found to be 5~<o per decade (slope}. This should provide a reasonably worst case approximation of beth coupler performance and possible current variation

ss ~ I effects due to power supply and bias circuit drifts. Thc temp'erature acceleration factor curve indicates this slope vsill be increased by 1.75 times at 55'C (AT), i.ess the slope will be 8.8'/ decade. The difference between 50 hours and 100,000 hours (t) is 3.3 decades (log 100,000 log 50), so the expected lower decile will provide about 29~io less light at 100,000 hours than initially. To provide the 10 mA output requirement, the IRED current must be raised by about 40/c to compensate for light lessening with operation ti.e, ] and this must be raised 100 29 by 18% (i,e., 1/.85) to compensate temperature variation of CTR, yielding a minimum input cur-rent to the IRED of 16.6 mA, as compared to the 10 mA required initially at 25'C. The formula used in this example is: 100 x x" 100 [slope x As x tog (t/50)] tsCfR/oT CTR where: s e AT is the temperature acceleration for slope at the expected operating temperature, CTR is the specified minimum current transfer ration, hCTR/>T is the change in CTR due to temperature, I;:- the required output current, is the required IRED bias current, Slope is the light output lessening per decade time, and t is the circuit design life. Note that for a one million hour life the required IRED current would only rise to 18.5 mA, as time has only increased by another decade! The estimate of the effect of operating time on the circuit has been almost as simple as the estimate of temperature effects. I20 IIO O g-IOO Cg. gt: 90 80 ~ TO a 60 50 -" ~o z W PEÃzE IOVe 90'0'A 1/>SzP'O ".e IO'4 MFG G MFG MFG M T COMPETITIVE COMPARISON, ACCELER*TED LIFE TEST MFG 40

~ \\ ~ ~ ~ ~ ~ s grr~xng auV nnn.itg t sensitive devices, except 'Fnv the tigh(senstttve pstsmct~ers. uch techniques are des 'h d, xcep 6r e ig i sensitive parameters. uch techniques are described m the General Electric Transistor manual and the General Electric SCR hlanual, and will;not be detailed here. The most common problem encountered is the leakage current measurement with the base open, as icqo is rarely measured on normal transistors, and understanding the need for considering dynamic effects and ambient light effects will solve the problem'. Dynamic effects must be considered, because the open base has no path but junction leakage to charge the junction capacitances. If the common high source impedance bias circuit for leakage current is used, the gain of the transistor multiplies the junction capacitance, of the collector base photodiode (= 25 pF), and provides a long stabilization time constant. Note the "double barreled" effect of source impedance in that it is the resistance in the RC time constant and also is the load resistor that determines voltage gain (A=l/hie. Rt ~ hFE). These effects indicate lczo should be measured by application of the bias voltage from a low impedance supply untiljunction capacitances are charged (now determined by the base emitter diode impedance), which can take up to 100 msec, (with no external capacitances, switches, sockets, coaxial, etc. connected to the base) in a darlington. After junction capacitance is charged, the current measuring resistor is introduced to the circuit by removing the short across it. The charge balance at the base can be affected by the motion of conductive objects in the

area, so best reproducibility will be obtained within an electrostatic shield. The electrostatic shield can also serve the purpose of shielding the detector from ambient light, the effects of which are obvious on a leakage current measurement.

Measurement of the light parameters of a phototransistor requires a light source of known intensity and spectral characteristics. Lamps with known spectral characteristics, i.evs calibrated standards, are available and, in conjunction with a thermo pile or calibrated photo cell and a solid mechanical positioning system, can be the basis of an opto measuring system. Some relatively simple systems based on the response of a silicon photo cell are available, but the assumption that all silicon devices have identical spectral response is implicit in their use for optical measure-ments. As different devices have different response curves, the absolute accuracy of these devices js impaired, although excellent comparative measurements can be made. Another method which has fair accuracy is the use of a calibrated detector, L9VX4 for the photo SCR's or L14H special for the phototransistors, to adjust tlie light source to the desired level. This willeliminate spectral problems as the calibrated device has an identical spectral response to the devices being measured". Accuracy will then depend on basic equipment accuracies, ambient control and mechanical posi-tion reproducibility. Spectral response measurements require use of precision filters or a precision monochromator and a calibrated photo cell or thermo pile. As in the case of the IRED, it is recommended that these measurements be done by a laboratory specializing in optical measurements. ~ C. Optocoupler Measurements The measurement of the individual devices in the optocoupler is identical to the measure-ment of a discrete diode and a discrete device ot the type of detector being considered, and is covered previously. The measurement of isolation and transfer characteristics are not as obvious, and will be illustrated.

g. /volation Paranierars are always measured with the terminals of each device of the coupler shorted.

This prevents the liigh capacitive cliarging currents, caused by the high dv/dt's applied during the measurement, from damaging either device. Safety precautions must be observed in these tests due to the very high voltages present! a). Isolation voltaee is measured as illustrated beiow. Niormally tlie surge voltage capability is measured, and, unless tlie higli voltage power supply has a fast shutdown (<0.5 @sec), the device under test will be destroyed if its isolation voltage capability is less than tlie high voltage supply 'ace "Avoid lCyO gttcsstgggmengs", ngndgiitg.

~ ~ ~ I I ~ ~ ~ p'he design guideline, unfortunately, is only valid for the G.E. IRED's and DIP couplers. Life tests of competitive units at both maximum rating and accelerated test conditions indicate a wide variation of performance exists in the industry. The accelerated test results were dupli-cated by the maximum'rating test results, indicating the same type of response in both the Ar and IFs/IFM curves. But the magnitude of shifts observed, especially the lower decile, are much greater, indicating much greater slopes, in percent per decade, of the light output vs. operating time graphs. This is illustrated in the plots comparing the life test results given above. To life cycle design with such devices would require derivation of a different model, based on a matrix of life tests. Based on extremely limited testing and some published information, it appears that at least two other manufacturers of IRED's and optocouplers can achieve light output perform-ance with operation similar to the G.E. performance. Neither utilizes the glass dielectric in the coupler and no tests have been performed to allow comment on other reliability factors. Degradation failure rates, to a desired criteria of percent initial light output, may be calcu-lated from accelerated data to use condition response by use of the design guideline. The design guideline temperature acceleration and slope per decade factors may be used to calculate an equiv-alent number of test hours at use condition to the accelerated test. Note that early hour slope of light output vs, time is very shallow, and accelerated test results are not valid for operating times under 168 hours. The number of devices which decrease in light output to a value less than the desired criteria on the accelerated test is then used with the equivalent unit hours to estimate 'ailure rate. IVhile this is not strictly accurate, due to the distribution of change in light output, the following is a useful approximation: log ~ x x AI + log 50] to X Agg t= 10 50) Ag2 where: Aq is the slope at stress conditions . slope at use conditions, AYq is the temperature acceleration at stress conditions, Aqz is the temperature acceleration at use conditions, t~ is the stress test duration, and t is the equivalent time at use conditions. The reliability test summary degradation failure rates were calculated this way and provide an example. The 100'C, 100 mA phototransistor accelerated operating life tests run for 168 hours (t ). The temperature acceleration curve gives a 'atio of the slope per decade at 100'C to the 55'C value of '=1.62. The middle line of the 1Fs/IF<<curve gives a ratio of=2.5 for the slopes 2.83 ~ ~, ~ 10 1.75 of a 10mA/10mA IFs/IF<<compared to the 100mA/10mA IFs/IFM the test was run at. Tl:e equivalent hours for this test at a 55'C use condition is: t= 10 ~ 50) f (log i x (1.62) x (2.5) + log 50] = 6770 hours. Two units of the 3 5 tested failed a light output criteria of half the initial value, giving a 2/2,200,000 device hours observed failure rate. which at the 50% UCL is the 0.12',"o per thousand hour failure rate shosvn in the summary chart. This also illustrates that for the G.E. IRED and coupler, the decrease in light output should have a minimal effect on circuit failure rate in con-servatively designe J circuits. 46

+.44 HIGH-VOLTAGE SUPPLY I I I IL ~ DIELECTRIC lSHIELO J O.U.T. I I I I E FOR VOLTAGES OVER 2500 Vrms, THE DIELECTRIC SHIELO IS RECOMMENDEO TO ELIMINATEAIR GAP EFFECTS. ISOLATION VO is set at. Crowbar techniques may be used in lab set-ups to provide rapid turnoff and forestall the test being described as "destructive." Steady-state isolation voltage is usually specified as a fixed percentage of the measured surge capability, although limited life tests indicate this de-rating is not required for the G.E. glass dielectric isolation. Application Engineering believes con-servative design practices are required in the use of isolation voltage ratings, due to the transients normally observed when line voltages are monitored and the catastrophic effects of a failure. b). Isolation resistance is measured at voltages far below the surge isolation capability, and has less potential for damaging the device being tested. The test is illustrated schematically here, O.U.T. ELECTRO-METER I I IL . MEASURING OF ISOLATION RESISTANCE t and requires the procedures normally used when measuring currents below a microampere. c). Isolation capacitance is a straightforward capacitance measurement. The capacitance of couplers utilizing the G.E. patented glass dielectric process is quite independent of applied voltage 49

I ,LN ST.lTF.t d ~ ee ~ ~ ~ m ~ ~ ~ ~ ' t I ~ F i,'m enomomm pJhrem .mA h ~ 0 o e ms esa e ~ ~ 'ne o' ~ u FEATURES: ~ Fast switching speeds ~ High DC current transfer ratio ~ High isolation resistance ~ 2500 volts isolation voltage ~ I/O compatible with integrated circuits ftndicttcs JEDEC tc istctcd valve t t I I t I $~ I photon CoupIed fsoIator 4M38"4N38A Ga As Infrared Emitting Diode 8; NPN Silicon Photo-Transistor The General Electric 4N38 and 4N38A consist of a gallium'rsenide infrared emitting diode coupled with a silicon photo~ transistor in a dual in-line package. d lion snt ml -'-I-Wpt- +to ~+ee anadem[st ~ ve t toe gS ~ ) ~ 4 ~ 'I $00 ~ CS I St ~to $ ~ 0 ltd sds ot F 0'0 tO $ 0 ~ Pdo Ol ~ 0 ~ OSOI I ~ t td I 0$ ooti oet'4$ SOO'td ~ ld tll ~ 0 .SCS I Se ISe OIS S ~ I Spl . ~ 00 ~ ~ $ tl~ ttl t ~pile ~ I 1 It ~costs I lee' seder le ~ ommmem edduesn os seem one moereeme ee ses oeeore>> eetsome ae ~ensue ~ t lammas s oosmoe send eouern Som ele mseeeee ~. %%me ~ lease oeeemmme mu roe suan md eom ~ 0 Peee deeeeo. absolute maximum ratings: (25 C) (unless otherwise speciTied) fStorage Temperature -55 to 150 C. Operating Temperature -55 to 100'C. Lead Soldering Time (at 260 C) 10 seconds. 4150 milliwatts 80 milliamps 3 ampere fTotal device dissipation 8 TA 4 25 C. PD 2SO mW. INFRARED EMITTING DIODE fPower Dissipation fForward Current (Continuous) fForward Current (Peak) '(Pulse width 300psec,2%duty cycle) t Reverse Voltage 3 volts <<Dcrate 2.0 mW/4C above 254C ambient. PHOTO.TRANSISTOR tPower Dissipation 44150 milliwatts tVcEo 80 volts tVCBO 80 volts tVEco 7 volts Collector Current (Continuous) 100 mBliamps 40Dcsatc 2.0 mW/4C above 2S4C ambient. fDcrasc 3.3 mW/ Cabovc 25 Cambicnt. individual electrical characteristics (25 C) INFRARED EMITTING DIODE fForward Voltage (IF ~ 10mA) fReverse Current (VR ~ 3V) Capacitance V~O,f< I MHz TYP. MAX. 1.2 1.5 100 50 UNITS volts microamps picofarads PHOTO TRANSISTOR t Breakdown Voltage V<SR>cEo (lc I mA, IF 0) t Breakdown Voltage V<aR)CSO (Ic I/EA, IF ~ 0) fBreakdown Voltage V(SRIEco (IE ~ I OOPA, IF ~ 0) fCollector Dark Current ICED (VCE = 60V, Ip ~ 0) tCollector Dark Current Icao (VCE -60V.I. -O) MIN. 80 80 TYP. MAX. 50 20 UNITS volts volts volts nanoamps nanoamps coupled electrical characteristics (25'C) MIN. TYP. MAX. UNITS t rotation V~olra e IDHg ertlh the input mrminai ~ idiodei shor(ed together and ihe output terminate Hransistor) shor ted toget her. tSaturation o)sage o lector mitter F = mA, C ~ mA Resistance IRED to Photo-Transistor (8 500 volts) Capacitance IRED to Photo-Transistor (80 volts, f= I MHz) DC Current Transfer Ration (IF ~ 10mA, VCE ~ 10V) Switching Speeds (VCE ~ 10V, IC, ~ 2mA, RI. ~ 100A) Turnn Time to TurneOff Time toff l27 4N38 1500 A 4N38A 1775 10 100 1 1.0 volts (peak) vo ts pea volts RMS sec volts giga ohms picofarad microseconds microseconds

Motorola offers a wide array of standard devices with 8 wide range of specifications (including the firstseries of DIP transistors and Darlington couplers to achieve JEDEC registration: transistors 4N25 thru 4N38, and Darlingtons 4N29 thru 4N33). AllMotorola couplers are UL Recognized with File Number E54915. CASE 730A IlIi I The Transistor Coupler is probably the most popular form ol isolator since it offers moderate ~ speed (approximately 300 kHz). sensitivity and economy. In addition, the collector-base junc-tion can be used as a photodiode to achieve higher speeds. The output in the diode mode is lower, requiring amplification for more usabte output levels. Gpticat Couplers/Isotators l 'i Couplers are designed t, . vide isolation protection fromhigh-vollage transients, surge voltage, or low-level noise that would otherwise damage the input or gen-erate erroneous information. They allow interfacing systems of difierent logic levels, different grounds, etc., that would otherwise be incompatible. ~Mti~rlt cou lersarelestedands ecifiedtoanisolati nv Ita Transistor Output olation Voltaoe is 7500 V Min ~eces. See nares. Device Type TIL112 TIL115 IL15 MCT26 TIL111 TIL114 IL'12 MOC1006 4N27 4N28 H11A4 TIL124 TIL153 IL74 MOC1005 TIL125 TIL154 4N25 4N26 H11A2 H11A3 H11A520 IL1 MCT2 TIL116. ~4N3 H11AS MCT271 H'I1AI H11A550 TIL117 TIL126 TIL155 CNYI7 MCT275 MCT272 MCT277 4N35 4N36 4N37 H11A5100 MCT273 MCT274 DC Current Transfer Ratio tys Mln 2.0 2.0 6.0 6.0 8.0 8.0 '10 10 10 10 10 10 10 12.5 20 20 20 20 20 20 20 20 20 20 20 20 30 45 50 50 50 50 50 62 70 75 100 100 100 100 100 125 225 V(8R) CEO Volts Mln 20 20 30 30 30 30 20 30 30 30 30 30 30 20 30 30 30 30 30 30 30 30 30 30 30 80 30 30 30 30 30 30 30 70 80 30 30 30 30 30 30 30 30 Darlington Output Isolation Voltage is 7500 V (Min) on ail devices. See notes. The Darllnglon Transistor Coupler is used when high transfer ratios and increased output current capability are needed. The speed. approximately 30 kHz, is slower than the transistor type but the transfer ratio can be as much as Ien times as high as the single transistor type. Device Type 4N31 H1183 4N29 4N30 MCA230 H118255 MCA255 H1182 MCA231 MOC119'IL119'IL113 MOC8030'IL127 TIL128'IL156 TIL157'1181 4N32 4N33 MOC8020'OC8050'OC8021'C Current Transfer Ratio s/ Min 50 100 100 100 100 100 100 200 200 300 300 300 300 300 300 300 300 500 500 500 500 500 1000 r n onn cted V(BR)CEO Volts Min 30 25 30 30 30 55 55 25 30 30 30 30 80 30 30 30 30 25 30 30 50 60 50 Notssi 1 tsoisooll surps vortsos,vtso,rs snrhtsrnstdsrlco d>stye trio OrssSdonnrstiny for inis isst LEO OInS i Snd 7 ~ r common snd phototi ~ hst ~ior pshs ~,5, ~ nd 6 sit coihmoll

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