ML13330B412
| ML13330B412 | |
| Person / Time | |
|---|---|
| Site: | San Onofre  |
| Issue date: | 10/21/1988 |
| From: | Medford M SOUTHERN CALIFORNIA EDISON CO. |
| To: | NRC OFFICE OF ADMINISTRATION & RESOURCES MANAGEMENT (ARM) |
| References | |
| NUDOCS 8810260173 | |
| Download: ML13330B412 (29) | |
Text
Southern California Edison Company P. 0. BOX 800 2244 WALNUT GROVE AVENUE ROSEMEAD, CALIFORNIA 91770 M.O.MEDFORD TELEPHONE MANAGER OF NUCLEAR ENGINEERING (818) 302-1749 AND LICENSING October 21, 1988 U. S. Nuclear Regulatory Commission Attention:
Document Control Desk Washington, D.C. 20555 Gentlemen:
Subject:
Docket No. 50-206 San Onofre Nuclear Generating Station Unit 1 By letter dated April 15, 1988, Amendment Application No. 150 was provided to the NRC which is in support of the replacement of the NIS at San Onofre Unit 1. As part of the NRC's review of the amendment application, questions were raised by the NRC reviewer. The questions and their responses are provided as an enclosure.
If you have any additional questions regarding this information, please let me know.
Very truly yours, Enclosure cc: J. B. Martin, Regional Administrator, NRC Region V C. M. Trammell, NRR Project Manager SONG 1 F. R. Huey, NRC Senior Resident Inspector, San Onofre Units 1, 2 and 3 8810260173 881021 PDR ADOCK 05000206 P
PNU4
Enclosure RESPONSES TO NRC QUESTIONS REGARDING THE NIS REPLACEMENT Question 1 In the NIS submittal, it is indicated that the replacement NIS is similar to the NIS in other Westinghouse plants with a few exceptions. What other plant is this replacement NIS similar to?
Response
There are over 70 Westinghouse plants with a similar 4-bay NIS system. The SO1 NIS is similar with the exception of the Intermediate Range which use an Intel 8095 microcontroller in the wide-range amplifiers. This channel provides Regulatory Guide 1.97 Post-Accident Monitoring functions at SO, which is unique. There are other plants in which components of the 4-bay NIS and Regulatory Guide 1.97 Post-Accident Monitoring systems share common areas (i.e., detector wells, conduit, penetrations, etc.).
These plants include Vogtle 1 and 2, Vandellos 2 and Shearon Harris.
The list of plants has been provided by Westinghouse in Attachment 1.
Question 2 A listing of the equipment provided as part of the NIS replacement indicates.
its status with regards to environmental and seismic qualification. Is all the equipment going to be qualified prior to plant start up?
Response
All required NIS upgrade equipment will have environmental and seismic qualification complete prior to plant startup. The seismic qualification is complete. The environmental qualification is complete by the supplier.
The final environmental qualification data packages are scheduled for SCE completion by December 30, 1988.
Question 3 Table 4.1.1 of SCE's submittal does not provide the plant modes for the surveillance. Does SCE intend to include the modes on this table?
Response
In the Description and Significant Hazards Consideration Analysis for Proposed Change No. 180 submitted to the NRC by letter dated April 15, 1988, it is indicated on page 3 that the modes for doing the surveillances are not included in Table 4.1.1.
The surveillances are covered by Specification 4.0.1 which states:
-2 "Surveillance requirements shall be met during the OPERATIONAL MODES or other conditions specified for individual Limiting Conditions for Operation unless otherwise stated in an individual surveillance requirement."
The operational modes for each of the items on Table 4.1.1 is provided in Table 3.5.1-1 also included in the April 15, 1988 submittal.
Question 4 On a loss of power followed by repower, does the system lose its memory and set points or is there an internal battery which would prevent this?
Response
On a loss of power followed by a repower, all of the NIS channels retain their setpoints because they are established by potentiometer settings. The Intermediate Ranges contain an Intel 8095 microcontroller within their wide-range amplifiers. The processing functions of the Intel 8095 are burned into the Programmable Read-Only Memory (EPROM).
Use of the EPROM prevents process memory loss and allows resumption of operation without loss of process ability.
The details of the microcontroller operation are explained in.
Question 5 Provide details on the Verification and Validation that is to be performed, such as who will do it, what program will be used and does it meet IEEE 7.4.3.2?
Response
Westinghouse has performed Software Verification and Validation (V&V) programs for safety-related I&C equipment utilizing embedded microprocessors. The particular program implemented for the San Onofre NIS wide range amplifier was a modification of a similar program covering wide range neutron flux monitoring at the Georgia Power Vogtle plant.
The Vogtle program was audited by the NRC to Regulatory Guide 1.152 and ANSI/IEEE-ANS-7-4.3.2 and the program was accepted as a part of that audit.
No unique Design/V&V plan was generated specifically for the San Onofre NIS; rather a plan was applied which had been used for a large scale V&V program for the South Texas Qualified Display Processing System and Georgia Power's Vogtle Site Plant Safety Monitoring System. This plan is a proprietary Westinghouse Specification 955842 which delineates the design, verification, and validation processes and the general activities that are to be used in the processes.
-3 The verification and validation activities were performed by a team of Westinghouse employees and consultants which were independent of the design organization, and in fact the San Onofre NIS verification team was constituted of the same individuals who were involved with the Georgia Power Plant Safety Monitoring System program which had been approved by the NRC.
Question 6 Provide details or an Operations Manual on the hardware such that the type of hardware being used can be determined (i.e., 65k machine, 8088 machine, etc.).
Response is also provided to give the details of the principle of operation of the NIS Intermediate Range wide-range amplifier which contains the Intel 8095 microcontroller. The excerpts are from the NIS Technical Manual supplied by Westinghouse for the NIS upgrade.
0411n
ATTACHMENT 1 WESTINGHOUSE MIS EXPERIENCE A total of 81 4-Bay Nuclear Instrumentation Systems have been provided to the following plants:
DOMESTIC UNITS Beaver Valley 1 Duquesne Light Beaver Valley 2 Duquesne Light Braidwood 1 & 2 Comonwealth Edison Byron 1 & 2 Coionweelth Edison Callaway 1 2 Union Electric Catawba 1 &2 Duke Power Comanche Peak 1 & 2 Texas Utilities
- 0. C. Cook 1 & 2 Indiana & Michigan Electric Diablo Canyon 1 & 2 Pacific Gas & Electric J. M. Farley 1 &2 Alabama Power Ginna Rochester Gas & Electric Indian Point 3 New York Power Authority Indian Point 2 Consolidated Edison Kewaunee Wisconsin Public Service McGuire 1 &2 Duke Power Millstone 3 Northeast Utilities North Anna 1 &2 Virginia Electric Power Co.
Point Beach 1 &2 WisconsinElectric Power Prairie Island 1 2 Northern States Power H. B. Robinson Carolina Power & Light V. C. Summer S. Carolina Electric & Gas Salem 1&2 Public Service Electric & Gas Seabrook 1 & 2 Public Service Co. ofN. H.
Sequoyah 1 & 2 Tennessee Valley Authority Shearon Harris 1 Carolina Power & Light South Texas Unit 1 & 2 Houston Li ghting 6 Power Surry 1 & 2 Virginia Electric Power Co.
Trojan Portland General Electric Turkey Point 3 & 4 Florida Power & Light Vogtle 1&2 Georgia Power Watts Bar 1 & 2 Tennessee Valley Authority Wolf Creek Kansas Gas & Electric Zion I & 2 Comonwealth Edison Total dTmestic units: 54
WESTINGHOUSE NIS EXPERIENCE INTERNATIONAL UNITS Angra dos Reis Furnas Brazil BR-3 SCK Belgium Tihange SEMO Belgium Takahama 1 Kansal Electric Japan Ohi 1 & 2 Kansal Electric Japan Mihama 1 Kansai Electric Japan Korea 5 & 6 Korea Electric Korea Ko-Ri 1 & 2 Korea Electric Korea Korea 7 & 8 Korea Electric Korea Napot Point Phillipines Phillipines National Power Corp.
Asco 1 & 2 FECSA Spain Almaraz 1 & 2 Central Nuclear de Almaraz Spain Vandellos 2 Assoc. Nuclear de Vandellos Spain Ringhals 2, 3 & 4 Swedish State Power Board Sweden Beznau 1& 2 NOK Switzerland Krsko NEK Yugoslavia Maanshan 1 & 2 Taiwan Power Taiwan Total international units: 27
ATTACHMENT 2' PRINCIPLES OF OPERATION 2-4-2-2 Wide Range Amplifier NM201. The wide range amplifier provides the signal conditioning and interface between the preamplifier and the Intermediate Range drawer bistables and isolation amplifier. Refer to Figure 2-5..
The wide range amplifier houses three printed circuit boards that perform all the necessary signal conditioning. The three printed circuit boards are:
o CPS/MSV Board NM201A o Test Signal Generator Board NM201B o Microprocessor Board NM201C The CPS/MSV Board NM201A is used in conjunction with the microprocessor board NM201C to use direct pulse counting techniques for the shutdown and startup modes of operation. By employing direct pulse counting techniques the wide range amplifier has improved statistical accuracy in the source range of operation (below 10-3% power).
The CPS/MSV Board NM201A.is used in conjunction with the microprocessor board to monitor the high accuracy.true RMS-to-DC converter circuitry over the oper ating range of 10- 3 to 200% power for the variance-signals.
The Microprocessor Board NM201C performs the logarithmic operation to combine the CPS (pulse mode) information with the MSV (variance mode) information to provide a dfift free output signal. that is proportional to the logarithm of reactor power over 10- to 200% power.
Access to the microprocessor board parameters is made through the D-connector J6 located-inside the wide range amplifier. A hand-held computer terminal is used in conjunction with a digital voltmeter to make all necessary adjustments for the alignment and-calibration.
By employing a microprocessor, the circuit drift associated with conventional analog logarithmic circuits is virtually eliminated.
2-39
CD EXISTING POWER ISOLATION EXISING O ERAMPLIFIER Ln RANGE B DRAWER WIDE RANGE INDICATION NM307 Ct- 0 ISOLATION (D 0 AMPLIFIER ODET A DET A COUNT D
03
-BPER NM306 SECOND HV 0LOSS OF STABLE HIGH
- aCABLE SEAL HVHIGH NC202AG ASSEM IES VOLTAGE
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m POWER SUPPLY RATE
(/3 tNO201 CIRCUIT (D
N00 R
S.
NM204 C) 0 HVI WIDETEST I
+DET 8
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2-5ECTION AMP TO RECORDER 0
FISSION J6 J4 -
NM201 WIE&-RATE 4
POWER AM IIER
-4 CHAMBER PENETRATION INTERMEDIATE RANGE MPLIFIER (D
BISTABLE
-CNC206 SUR TRIP IA HIGH SUR INTERMEDIATE NC203 ROO RANGE DRAWER TRIP SOURCE RANGE (D
BISTABLE NC205 CUTOFF 0
(D
PRINCIPLES OF OPERATION 2-4-2-2.1 CPS/MSV BOARD NM201A. The CPS/MSV board NM201A has two operating channels that.monitor a wide range of reactor power. The-first channel pro vides counts per second (CPS) pulse signals covering a range of 10-1 to 106 CPS. These are passed through a.discriminator to reject alpha and gamma pulses. The discriminator is a high-speed differential comparator, which compares the input signal to an adjustable discriminator voltage. Pulses greater than the discriminator voltage level are counted. A prescaler controlled by the microprocessor board divides the pulse count rate by 2 or 8.
The prescaled pulses are then counted by the processor board for conversion to the logarithm of the count rate.in the units of counts per second (CPS).
The second operating channel on the CPS/MSV board monitors the reactor power level between 10"
%power and 2 x 102 % power with a MSV (variance) measurement of the detector signal.
The input signal is fed through a digitally controlled gain amplifier and a band pass filter (10 kHz to 100 kHz).
The resulting signal goes to a RMS to DC converter that yields a DC voltage output signal proportional to the root mean square of the input voltage. The digitally controlled selectable gain stage assures operation of the RMS to DC converter within a favorable range for the full range of input signals. This RMS voltage is squared digitally to obtain the MSV signal proportional to the logarithm of percent reactor power.
A detailed description of the CPS/MSV circuit is as follows:
CPS/MSV BOARD NM201A CIRCUIT DETAILS CPS Circuit The input (TP2) to the CPS board pulse counting circuit is also connected to the input terminating resistor R33 shown in the schematic.for the MSV circuit.
The CPS circuit is shown on Sheet 2 of the diagram schematic; and the MSV circuit is shown on Sheet 1 of the same diagram in Section 10.
An input resistor divider R41 and R58 attenuates the input pulse.signals before being clamped by diodes D1 and D2.
This 'attenuation permits full swing of the input 2-41
PRINCIPLES OF OPERATION signal without adverse clipping at maximum MSV input levels. Capacitor C31 (20 pfd) filters very high frequency noise signals. The positive polarity input pulse signals are capacitively coupled via capacitor C38 to input pin 14 of
.wide-band differential. amplifier Ull.
Resistors R57 and R68 provide balanced DC biasing of amplifier Ull.
Pins 3 and 12 of U11 are connected together to give a Ull single-ended voltage gain of approximately 40. This, combined with input resistor voltage divider R41 and R58, yields a nominal AC gain of 8 from input to output pin 8 of Ull.
The amplified input pulse at pin 8 of U11 nominally ranges in amplitude from 0.2 Vp to 2.0 Vp. These signal pulses are AC coupled through capacitor C37 to a baseline restoration circuit consisting of transistors Q4, Q5, Q6, Q7 and resistors R44, R46, R51, R52, and R67. This circuit provides a zero voltage baseline reference for the amplified negative going variable amplitude pulses presented to negative input pin 4 of high-speed comparator circuit U9.
The output of comparator U9 is normally at -0.6 volts DC. When a pulse signal goes below the threshold level set at pin 3, the comparator output goes positive to a nominal voltage of +3 volts. Positive voltage feedback of approximately 35 C
millivolts is provided at U9 pin 3 through resistor R50. This positive feedback effectively stretches the comparator output pulse and provides positive drive to the base of the transistor 41.
Transistor Q1 provides voltage translation of detected pulses to clock the input of counter circuit U8.
Integrated circuits U8 and U10 provide a mechanism to divide the detected pulse by either 2 or 8 as determined by the level of the CPS/8 input signal.
Binary counter circuit U8 divides the clock pulses by 2 at U8 pin 3, and by 8 at U8 pin 5. The resulting square wave signals are connected to pins 11 and 8 of analog multiplexer U10, respectively. When pins 5 and 6 of U10 are held low by the output of buffer quad op amp U6 pin 1, UlO pin 11 is internally connected to U10 pin 10, which yields a divide by 2 square wave output at PULSES OUT (Pl 16a and 16b) and test point and CPS/MSV board.T1 PULSES OUT. Similarly, when UlO pins 5 and 6 are pulled high by the CPS/8 input signal a divide by 8 square wave output is generated.
2-42
PRINCIPLES OF OPERATION The adjustment for CPS discriminator voltage level is provided by DISC ADJ potentiometer R. Test point TP3 DISCR. VOLTS is provided for measuring the discriminator voltage level.
Factory testing has demonstrated that a discrim inator voltage setting at -1.00 volts dc provides the optimum signal-to-noise ratio while rejecting unwanted gamma and noise pulses. The discriminator voltage at test point TP3 is 6.11 times larger than the actual threshold applied to pins 3 of U9.
MSV Circuit Refer to Sheet 1 of the schematic diagram for the discussion of the MSV circuit. The input to the MSV circuit at J215 SIGNAL INPUT is provided across resistor R33 and the series combination of R41 and-R58 at the input of the CPS circuit..This properly terminates the 75 ohm triaxial cable carrying the output signal.from the preamplifier. The input signal is coupled through a single-pole high-pass filter C25-R31 to the input of the first three-pole low pass active filter comprised of amplifier-US, resistor R28, R29, R30, and capacitors C12, C13, C23, and C24.
Resistor R12 and capacitor C22 provide compensation for US preventing uncontrolled amplifier oscillations. Similar compensating networks are provided for amplifiers Ul, U2, and U4. The output of this low-pass filter (pin 6 of US).is fed to a three-pole high-pass active filter stage. Amplifier U4 combined with capacitors C9, C20, C21, and resistors.R10, R11, R27 provide this high-pass function.. An adjustment voltage gain is provided in this amplifier stage as determined by the voltage divider R27 and R9 plus resistor R26. The potentiometer R26 is set at the factory for 4.000 volts RMS at test point TP2 at 100 percent power using an MSV test signal voltage of 1.350 volts on TSG board NM201B.
The signal at pin 6 of U4 is coupled via C45-R70 to a computer controlled gain amplifier stage comprised of 8 bit buffered multiplying 0/A converter U3 and amplifier stage U2. These two devices provide a controlled gain between input pin 16 of U3 and output pin 6 of U2 in response to digital control signals on pins 4, 6, and 8 of U3.
In this application, only one of these control signals is allowed to be high at any give time. The resulting MSV circuit voltage gains are:
GAIN = 1 for U3 -
pin 8 high, GAIN.= 4 for U3 -
pin 6 high and. GAIN 2-43
PRINCIPLES OF OPERATION
= 16 for U3 -
pin 4 high. The processor board NM201C controls the gain to the MSV circuit to optimize the range of the signals out of the RMS-to-DC converter U7. The processor GAIN control signals to the MSV circuit are displayed on LEDS 0S4 -
GAIN = 1, DS3 - GAIN = 4, and DS2 - GAIN = 16.
Buffer amplifier U6 is used to buffer the control signals to U3.
The output of gain stage amplifier U2 pin 6 is fed to a second three-pole low pass.active filter comprised of amplifier Ul, resistors R22, R23, R21, and capacitors C17, C16, C3, and C4. The output of this filter stage (Ul pin 6 is then coupled to RMS-to-DC converter U7 through high-pass filter C15-R20. U7 is a wide band RMS-to-DC converter circuit that-provides rms conversion of the amplified input signal (10 kHz to 100 kHz'bandpass filtered) to yield an essentially DC output voltage signal (MSV out) proportional to the input signal.
Capacitor C32 (1 microfarad) sets the response time of this converter circuit to approximately 0.07.seconds. The RMS-to-DC converter output is provided at MSV OUT (Pl-18a and 18b) and test point TP2 MSV.
Power supply voltages +15 volts DC and -15 volts DC are provided through, connector pins P1-8a, P1-8b and P1-10a, P1-10b, respectively. Bypass filtering is provided by capacitors C41, C42, C43, and C44. Additional resistor capacitor filtering of the +15V and -15V supplies is provided to each active amplifier circuit to assure stable oscillation-free operation of the MSV circuit.
2-4-2-2.2. TSG BOARD NM201B The wide range amplifier Test Signal Generator (TSG) board NM201B generates test signals for the preamplifier. The TSG provides test signals to the preamplifier which are controlled by the Intermediate Range drawer OPERATION SELECTOR switch position.as decoded by the Interface Module NM203. The TSG signals provide a means of verifying the proper operation of the Intermediate Range channel from the drawer to the preamplifier and back to the drawer.
2-44
PRINCIPLES OF OPERATION A detailed description of the TSG circuit is as follows:
TSG BOARD NM20.B CIRCUIT DETAILS TSG Circuit The test signal generator (TSG) circuit shown in schematic diagram, Sheets 3 and 4 in Section 10, provides a set of controlled test signals that are transmitted to the wide range preamplifier via triaxial cables. These test signals.are controlled in response to control signals from the Interface Board NM203. Three CPS test signals that correspond to 101.
10.3, and 105 counts per second can be selected along with MSV test signals of 102, 100, and 102 power. -Provisions are.made to individually adjust both CPS and MSV test signal levels by trimpots on this board. The test signal is coupled to the output connector though a relay contact that is closed only when test signals are requested., The circuit also provides a DC bias current through the output that energizes a test input relay K1 in the preamplifier when 'a test function is selected.
The test signal generator circuit has three primary functional parts. The first of these is a test pulse control function; the second is a high frequency buffer amplifier section; and the third is a simple decoder and relay driver section that energizes the output relays.
Test Pulse Control The test pulse control section is comprised of:
1 megahertz crystal oscillator Y1, dual BCD counter circuits U2, U4, U8, triple three-input AND gate circuits U3, U5, and analog multiplexers U9 and U10. The output of the 1 megahertz crystal oscillator Y1 is fed to the enable input of BCD counter U8 pin 2 to increment the first counter every negative transition of the one megahertz.
signal. The Q3 state of this'first counter generates a 2 microsecond positive pulse every 10 microseconds at U8 pin 6. This is the 105 CPS gate signal and is used to clock dual counter circuit U2 and as an input to analog multiplexer U9 pin 14. 'Outputs from dual counter U2 are fed to triple three-input AND gate 2-45
PRINCIPLES OF OPERATION circuits in U3 which produce a positive going 2 microsecond wide pulse at a repetition rate of 103 pulses per second. This is the 103 CPS gate signal which is connected to analog multiplexer U9 pin 15, dual counter U4 pin.2, and AND gate circuit US pin 3. U4.and U5 are interconnected like U2 and U3 to yield a 101 CPS gate signal at US pin 9 which is fed to analog multiplexer U9 pin 12. A 50 kHz square wave MSV gate signal is generated at pin 11 of dual counter U8.
The desired CPS or MSV gate control signal is multiplexed to pulse amplifier gate transistor Q3 through resistor capacitor combination R13, R14, C2 when any one of six test signal modes is selected. Capacitor C2-assures rapid turn off and turn on of transistor Q3.
The selection of 101 CPS, 103 CPS, 105 CPS, or the 50 kHz MSV gate signal is determined by the binary state of digital control lines A, B, and C (connector P3 pins 4, 6, and 8 respectively). Resistors R7, R9, R8 provide pull up of these signals when not selected. The table in the schematic diagram, Sheet 3 gives the test signal selection versus status of control signals A,. B, and C.
The base amplitudes for the CPS and MSV test signals are controlled respectively by trimpots R43 CPS AMP ADJ :and R46 MSV AMP ADJ. Test points for the CPS test voltage amplitude are CPS AMP TP2 and TP1 and test points for the MSV test voltage amplitude are MSV AMP TP3 and TP1-. These signals are fed to analog multiplexer U10 and imposed'upon U10 pin 3m response-to control signals A, B, and C at pins 11, 10, and 9, respectively. The selected amplitude control signal transmitted to the noninverting input of buffer amplifier U11 through resistor.capacitor combination R16, C4. Amplifier U11 is the amplitude control input stage of the high frequency buffer amplifier.
High-Frequency Buffer Amplifier The high-frequency buffer amplifier provides an AC gain of -1 in response to the selected gate control signal and amplitude control signal.
Quiescent biasing of approximately 5 mA in both output transistors Q7 and Q8 is provided.
A nominal 5 mA current source is generated at the collector of transistor Q6 by 6.2 volt Zener diode 06 and 1.11 Kohm emitter resistor R29. Five (5) mA 2-46
PRINCIPLES OF OPERATION flowing through the 20 ohm resistor.R35 is matched by the 5 mA in 10 ohm resistor R38 and R39. Diodes 04 and 05 provide voltage matching for the base emitter drops of transistor Q7 and Q8. A nominal current source of 8 mA is generated at the collector transistor Q4. This current source is set by transistor Q5 and resistor R26, R27, and R28. Eight (8) mA are set in transistor Q5 as determined by the +15V DC supply divided by the sum of 100 ohm resistor R26 plus 1.75 kohm resistor R28. Resistor R27 matches R26, which fixes the current through R27 at 8 mA. This 8 mA current source must be greater than the 5 mA current source to guarantee proper biasing through-diodes 03,.04, and 05 and resistor R35. The excess bias current must flow through either diode D2 to the amplitude control voltage set by buffer amplifier U11, or through diode 01 when transistor Q3 is turned on.
The buffer amplifier generates negative-going 2 microsecond wide CPS test pulses when CPS test pulses are requested. With transistor Q3 turned off, the amplitude of the test pulse is set by the voltage at pin 6 of buffer.amplifier Ull.
Resistor capacitor combination R25-C16 (10 ohm and 1 mfd) provide decoupling.of this amplitude control signal.
Diode 06 is forward biased with 3 mA flowing through 35.7 ohm resistor R22. Resistor R22 is chosen to provide the approximate voltage drop that is present across transistor Q3 when it is turned on. When transistor Q3 is turned on, diode 01 conducts and diode D2 blocks. The result at the common cathode connection of diodes 01 and D2 and at the buffer amplifier output (common connection of R38 and R39) is the desired negative going CPS test pulse. MSV test signals are generated with a 50 kHz square wave drive to Q3 and buffer amplifier Ull amplitude controlled to the MSV test voltage level.
Rise and fall times achieved.at the output of this high frequency amplifier are approximately 100 nanoseconds.
Decoder and Relay Driver A decoder and relay driver function control relays K1 and K2 to couple the test pulse signals to output connection pins P3-32a and 32b. Logic gate circuits decode the status of control signals A, 8, C to drive relays K1 and K2 through transistors Q1 and Q2, respectively. The schematic diagram shows the relay contacts in their de-energized states. The relays are energized as a function 2-47
PRINCIPLES OF OPERATION of signals A, B, and C.as shown in the table of the schematic diagram. For CPS test signals, relay K1 is energized and test pulses are transferred through resistors R31, R32, R37, R41, and capacitor C18 to the output. Three levels of MSV signals are generated by the combination of relays Kl, K2 and attenuating resistors R37, R31, R32, R40, R23, and R24 to yield MSV test signals where the output amplitudes are:
10-2% = 0.1 x 10% amplitude and 10% = 0.1 x 102 %
amplitude. In addition, a negative DC.bias.current of approximately 26 mA is generated by 500 ohm-resistor R36 when either K1 or K2 is closed and the test signal generator is connected to preamplifier. Test point TP4 TEST SIG is the output of the TSG amplifier that is applied.to the preamplifier.
2-4-2-2.3 Processor Board NM201C. The processor board is the heart of the wide range amplifier. The processor board employs a 8095 Intel microcontroller for performing the operations. The processor board includes 2K x 16 of random access memory (RAM), 8K x 16 of Programmable Read-Only Memory (EPROM), 16 parallel input/output (1/0) lines, four 10-bit analog-to-digital (A/D) converters, two 12-bit digital-to-analog (D/A) converters and the capability of handling RS-232 serial communications.
The processor board controls the operation of the wide range amplifier and performs the following functions:
o Receives, controls,.and-processes the MSV and CPS signals from the CPS/MSV board NM201A o Controls calorimetric gain and scale constants o Drives the drawer meter, bistables, and isolation amplifiers o Performs RS-232 serial communication with hand held terminal for alignment and calibration The principles of operation for the processor board NM201C is divided into two sections: hardware operation and software operation.
2-48
PRINCIPLES OF OPERATION The hardware description is as follows:
Processor Board NM201C Circuit Details Refer to Sheets 5 and 6 of the schematic diagram of the processor board. The processor board uses an Intel 8095 microcontroller, Ul.
U1 has four A/D channels ACH4, ACH5, ACH6, ACH7 and a high speed serial port HSI1.
The processor operates at a clock frequency of 12 MHz as determined by crystal Y1 and capacitors C3 and C4. The processor also has 16 bidirectional address/data lines ADO through AD15 that are used for on-board addressing and control. The description of the processor board operation is broken down into the following subsections:
o Memory Organization o CPS Interface o MSV Interface o Analog References and Adjustments o RS-232 Communication Interface Memory Organization Refer to Sheet 6 of the schematic diagram. U1 fetches data and instructions from the bidirectional address/data lines ADO through AD15 using a two cycle fetch. During the first cycle of the fetch, processor U1 places the desired address on lines ADO through AD15 while also making U1 control signal ALE (address latch enable) high. Octal latches U4 and U5 are connected to the ADO through AD15 lines and are-enabled by the ALE signal to hold onto the processor requested.address. During the second cycle of the fetch, processor U1 changes the state of the read/write control lines RD and WR to either transmit or receive instructions or data from the device selected by the address lines MAO through MA15 at the output of the' latches U4 and US.' After the second cycle is complete, the processor starts a new cycle and repeats the process as required.
U2 (a 1 out of 16 decoder is used to activate the various memory chips and memory mapped devices. The upper four latched address lines are decoded thus 2-49
g PRINCIPLES OF OPERATION dividing the total 64K addressable space into 4K sections. The blocks have the following assignments.
SIG ADDRESS USAGE YO OOOOH Not used Y1 1000H RAM Y2 2000H PROM Y3 3000H PROM Y4 4000H PROM Y5 5000H PROM Y6 6000H Latched Outputs to Test Signal Generator Board Y7 7000H Operation Selector Switch Inputs Y8 8000H D/A 1 Converter Y9 9000H O/A 2 Converter Y10 AOOOH Not used SIG ADDRESS USAGE Y11 BOOOH Not used Y12.
COOOH Not used Y13 DOOOH Not used Y14 EOOOH Not used Y15 FOOOH Not used All of the decoder lines are high when they are inactive. U3 is a four input NAND gate with its output held low (logic 0) when the decode lines 2000 through 5000 are high. Anyone of the four-decodes lines going low causes its output to go high and provide the chip select for the EPROMs.
Each of the 16 bit wide RAM and EPROM spaces are covered by.two 8 bit wide ICs.
The fields are word oriented in which the even numbered bytes are in one IC and the odd bytes are in the other IC. U1O is the even or lower RAM IC, and U9 is the odd or upper RAM IC. U8 is the even or lower EPROM IC, and U7 is the odd or upper EPROM IC.
- 2-50
PRINCIPLES OF OPERATION Both EPROMs are enabled when both the processor RD line and EPS line from U3 are high. The processor takes in a word and will discard the unwanted byte if only one of the two bytes of the word is required. Likewise, both of the RAM ICs will be read when both the RS (decoder line Y1) and the processor RD lines are high, with the processor discarding the unwanted byte from the-word read for byte operations. To avoid overwriting unwanted bytes, each of the RAM IC's are enabled individually as needed for write operations. U13 combines the processor WR signal with the LBE signal (AO latched) to form the LWE signal which enables the even or lower RAM IC.. Another gate in U13 combines the HBE signal from U6 (processor BHE signal latched by U6) with the processor WR signal to form the HWE which enables the odd or upper RAM IC. With these signals, the processor will enable the correct IC for byte writes and will enable both for writing words.
CPS Interface Pulses from the CPS circuit on CPS/MSV board NM201A P1-16a and 16b are input to the processor board NM201C at P4-18a and 18b. Resistors R17 and R18 scale the pulse amplitude from approximately 5.0 volts to 4.00 volts. Schmidt trigger U17 receives scaled pulses and transmits dutput pulses to processor U1, pin 4 for the high speed input line HS11. The processor algorithms used to convert the random pulses into the CPS count rate level are described in the software description.
The processor Ul also controls the count rate 'that is transmitted to the HSI1 input port by providing a divide-by-8 signal to CPS/MSV circuit to divide the incoming pulse repetition rate by 8. The processor DIV BY 8 control signal at P4-20a and 20b is initiated by U2 control sighal Y6 which is held low with processor WR line for controlling gate U13. The output of U13 is inverted by flip-flop U17 and is used by latch U1l.
When the proper address selection (6000H) is given, the four lowest bits ADO through AD3 are latched into U1l.
The output of Ull is wired to quad op amp Ul2 for shifting the control signal voltage from +5 volts to +15 volts required by the CMOS logic on the CPS/MSV board NM201A.
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PRINCIPLES OF OPERATION MSV Interface The MSV voltage from the MSV circuit on CPS/MSV board NM201A P1-18a and 18b is input to the processor board NM201C at P4-16a and 16b. Resistors R15 and R16 scale the.input voltage by the ratio of five-sixths to prevent saturation of the processor A/D converter at 200 percent power conditions. The voltage from the resistor network is connected to processor Ul, pin 43 for.the processor A/D channel 4 (ACH4). The processor algorithms used to convert the MSV voltage into the MSV PERCENT POWER level is described in the software description.
The processor Ul controls the gain of the MSV circuit by providing three control lines GAIN 1, GAIN 4, and GAIN 16 to the CPS/MSV circuit. The processor gain control signals are initiated by U2 control signal Y6 which is heldlow with processor WR line for controlling gate U13. The output of U13 is inverted by flip-flop U17 and is used by.latch Ull.
When the proper address selection (6000H) is given, the four lowest bits ADO through AD3 are latched into Ull.
The output of Ull is wired to quad op amp U12 for shifting the control signal voltages from +5.volts to +15 volts required by the CMOS logic on the CPS/MSV board NM201A.
Analog References and AdJustments Power supply voltages +5 V, +15 V and -15 V are filtered by capacitors C20, C21, C22, C23, C37 and C38 and inductors Li and L2. Voltage reference U15 provides a precision voltage reference for 0/A converters U21 and U22, processor Ul, and potentiometers R9, R11, and R13.
Potentiometers R21 D/A-1 ADJ and R24 D/A-2 ADJ divide down the Ul5 reference voltage. The wipers of potentiometers R21 and R24 are connected to quad op amp U16B and U16C respectively. Amplifiers U16B and U16C are connected as non inverting amplifiers with a gain of 1.2 defined by the ratio: 1 + R20/R19 or 1
+ R23/R22. By using the amplifiers U16B and U16C, the D/A converter outputs at U21.and U22 can be adjusted up to 12 volts at full scale.
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(g)
PRINCIPLES OF OPERATION Resistors R4 and R5 divide the U15 reference voltage from +10 volts to +5 volts. Op amp Ul6ktogether with transistor Q1 form a buffered +5 volt reference. The emitter of Q1 is wired to processor U1 A/D converter reference VREF at pin 45 and to adjustment potentiometers R9 CPS GAIN, R1 MSV GAIN and R13 BACKGND. The wiper of the potentiometers R9, R11, and R13 are connected to processor U1 A/D input channels ACH6, ACH7,, and ACH5, respectively.
Adjustment potentiometer R9 CPS GAIN is monitored by the processor U1 and is used to adjust the amount of overlap-between the CPS and MSV signals. The adjustment is set.at the factory for 1.00,as read on the hand held terminal or 2.50 volts at test point TJ1.
Adjustment potentiometer R11 MSV GAIN is mon-itored by the processor Ul and is used to adjust the wide range percent power indications until they agree wit calorimetric-measurements. The 0 to 5 volt voltages at the potentiometer wtper (and test point TJ2) are used by the processor-as gains from 0.1 to 10.0, respectively. A voltage of 2.50 volts at test point TJ2 corresponds to a gain of 1.0' Adjustment potentiometer R13 BACKGND is-monitored by the processor Ul and is used to eliminate alpha and noise contributions in the MSV signals below 102 CPS. The Oto 5 volt voltages at the potentiometer wiper (and test point TJ3) are used by the processor as a 0 to 50 millivolts discriminator.
D/A-2 converter U22 is controlled by the Intermediate Range drawer OPERATION SELECTOR switch S201 position. If the selector switch is in the NORMAL position, the output of D/A-2 U22 corresponds to the.wide range percent of reactor power over 10 7.to 200%. If the selector switch is in.the MSV LOCAL position, the output of 0/A-2 U22 corresponds to the MSV percent power 10- to 200%. Finally, if the selector switch is placed in the CPS LOCAL position, the output of D/A-2 U22 corresponds to the CPS count rate level over 10-1 to 106 CPS. The D/A-2 output of P4-30a and 30b is connected to the Interface Module NM203 for distribution to the drawer panel meter.
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PRINCIPLES OF OPERATION 0/A-i converter U21 output is always the wide range percent of reactor power over 10 to 200% power. The D/A-1 output at P4-32a and P4-32b is connected to the Interface Module NM203 for distribution to the drawer start up rate amplifier, bistables, and isolation amplifier.
The processor control of the D/A converters is.determined by the OPERATION SELECTOR switch which is read by Interface module NM203 and is read by U14.
Resistor pack R3 pulls the five input lines on terminals P4-2a and 2b through P4-8a and 8b to +15 volts if the control lines are not selected. Resistor packs R1 and R2 divide the incoming +15 volts down to +5 volts required for CMOS circuits. The status of the switch is read when U2 control line Y7 and the processor read line RD go low at the same time; bus driver U14 inputs the selector switch control lines..
The D/A converter U21 provides an output on D/A-1.when the processor Ul selects memory address 8000H and gate U20 combines U2 control line Y8 or D-Al with the processor Ul write signal WR to enable D/A converter U21. The D/A converter U22 provides an output on D/A-2 when the processor Ul selects memory address 9000H and gate U20 combines U2 control line Y9 or D-A2 with processor U1 write signal WR to enable D/A converter U22.
RS-232 Communication Interface The processor U1 has two RS-232 interface lines Rx0 (pin-1) and TxD (pin 2) for receiving and transmitting data to and from the HT-1000 hand held computer terminal and the processor board serial data circuitry. U18 is an interface circuit that translates the processor U1 +5 volt TxD signals to levels required by RS-232 convention. U19 provides an interface circuit that receives incoming data from the hand held terminal at the RS-232 voltages and converts them to +5 volt RxD signals for the processor Ul. The communication between the processor board NM201C and the hand-held computer terminal is designed for a 9600 bits per second baud rate.
The information available on the HT-1000 hand-held terminal displays and the HT-1000 set-up requirements are given in the following sections:
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PRINCIPLES OF OPERATION Hand-Held Terminal' Operation Terminal Initialization Before plugging the hand-held terminal into J6 connector provided for it on the Wide Range Amplifier NM201, the terminal itself must be programmed. The wide range amplifier has been designed to use a HT-1000 Termiflex terminal.
Since there are several models available, it will be necessary to consult the instructions that come with the terminal to determine the correct procedure and nomenclature that applies to the particular terminal to be used. The following is a listing of the parameters to be set.
Some terminals will not require some of the parameters on the following list.
COM - Communication Options Baud Rate Line 9600 Bits per second Baud Rate XFR 9600 Bits per second Parity Line Even Parity XFR Even Echo Characters No Display Parity Error No Audible Parity Error No Auto X OFF No Append LF No STX ETX No DSP - Display Options Flashing No Display.CTRL CHAR No Save No Linear Memory No 2-55
PRINCIPLES OF OPERATION KB0 - Keyboard Options Auto'Key Repeat No Maximum Key Repeat No Disable Keyboard Shift No Audible Keys No Program Functions Not used - may use default or any characters as needed for other applications Terminal Operation To initiate terminal operation, simply plug terminal into J6 connector provided under the inside of the Wide Range Amplifier NM201 lid and depress the ON button.. The desired screen is obtained by first pushing key 2 and then by pressing the key for desired screen number. Only the keys 1 through 5 are active. Pressing any other key will not have any effect on what is being displayed. The selected information will appear within approximately one second of depressing one of the keys 1 to 5. After depressing one of the selection keys, the data portion of the screen updates once every second. The legend part of the screen is written only when a new key is depressed. When the terminal is plugged in, data corresponding to the last key that was depressed may appear on the screen without a legend. Pressing a different key will bring up a-legend and its corresponding data. Thereafter, the legends and corresponding data will appear on the screen. After depressing an inactive key (0 or 6 through 9), the data and legend for the last chosen screen remains without data updating.
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PRINCIPLES OF OPERATION There are five screens that may be viewed.
Screen 1 CPS Counts per second in exponential form SCALER Counts for.1 second Screen 2 CPS Counts per second in exponential form SCALER Counts for 1 second Screen 3 CPS Counts per second in exponential form SCALER Counts for 10 seconds Screen 4 MSV Percent Power RMS Input Voltage BACK Background Noise Potentiometer Voltage GNMSV MSV Gain Setting Screen 5 WRPR Wide Range Power WRCPS Wide Range CPS Voltage WR_MSV Wide Range MSV Voltage GNCPS CPS Gain Setting 2-57
PRINCIPLES OF OPERATION Processor Board NM201C Software Details Refer to Sheet 7 of the schematic diagram in Section 10 of the processor board software. The-processor board software operational description is broken into the following subsections:
CPS Level Calculations MSV Level Calculations Wide Range Power Splicing Calculations CPS Level Calculations The processor continuously counts the number of pulses that are received from the CPS/MSV board NM201A at the processor HSI1 high speed serial port.
Eight times a second the processor reads the number of counts and stores the value in memory as the variable CSUM.
The procedure CPS CALC adds the number of pulses received in a number of C
previous 0.125 second intervals until a required quantity is found. 'The quantity is based on the number of counts needed to have good Poisson counting statistics. The time interval over which the pulses occurs is placed in the variable ISUM. The unfiltered count rate is calculated by the procedure SCALE.
The procedure SCALE provides a scaler count rate for the most recent fixed time.,
intervals-of 0.1, 1.0 or 10.0 seconds. This output is displayed on the hand held computer terminal screens 1, -2 and 3 for calibrating the CPS/MSV board NM201A CPS circuits.
The procedure CPS CALC -also computes the filtered count rate, CR, that is calculated by-the number of pulses CSUM divided by the amount of-time in seconds ISUM to count minimum number of pulses. The filtered CPS level is available on the hand-held terminal screens 1, 2 and 3 over the range of 0.10EO to 1.00E6 (10-1 to 106) CPS.
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PRINCIPLES OF OPERATION The log to the base 10 of the count rate, CR, is calculated by the procedure LOG2W and is scaled for the D/A-2 output when the Intermediate Range drawer OPERATIONAL SELECTOR switch S201 is in any of the CPS test positions (101 CPS, 103 CPS, or 105 CPS).
At count rates above 100,000 CPS, pure analog pulse counting electronics have significant counting losses due to pulse pile-up. With the microprocessor, the count rate CR is compensated to correct for counting losses by a dead-time correction algorithm which places the corrected result in the variable CR 0.
The log to the base 10 of the corrected count rate, CR D,, is calculated by the procedure LOG2 0 and is scaled for the D/A-2 output when the Intermediate Range drawer OPERATION SELECTOR switch S201, is in the CPS LOCAL position.
The procedure CPS CALC finally computes the wide range percent power equivalent of the CPS level as the variable CPS G., The procedure computes the CPS G variable value by'computing the log base 10 of the corrected count rate CR D multiplied by the CPS GAIN setting GN C and the MSV GAIN setting GN M. The CPS G variable is then scaled as the value WR CPS which is sent to the splicing procedure. The WR CPS value is also available on the hand-held terminal screen 5 as a voltage scaled by the procedure volts.
The procedure GN IN converts the CPS GAIN ADJUST potentiometer R9 voltage to the equivalent gain factor GN C.- The GN C value is-available on the hand-held terminal screen 5 as GN CPS and is set at the factory at 1.00.
MSV Calculations The processor receives RMS voltages from the CPS/MSV board NM201A on A/D channel 4 where the A/D result is-stored in the variable RMS. The RMS voltage from the CPS/MSV board also includes intrinsic noise from the electronics and alpha activity in the fission chamber, BN. The RMS voltages are corrected by the procedure BKGND.
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PRINCIPLES OF OPERATION In the procedure BKGND, the processor reads the BACKGND adjust potentiometer R13 voltage and stores the result in the variable VBN. The RMS reading is corrected for background noise as the difference between the square of the RMS value minus the square of VBN. The noise corrected RMS value, RMS NC, is calculated by taking the square root of the above result.
In the procedure MSV CALC, the processor computes the MSV percent power level LOG MSV by computing the log base 10 of the squared RMS NC variable multiplied by the MSVGAIN setting GN MSV. The MSV percent power level is provided on the
-3 hand-held terminal screen 4 over the range of 1.OOE-3% to 2.OOE+2% (10 to 200%) power. The LOG MSV variable is then scaled as the value WR MSV which is sent to the splicing procedure and is also output on D/A-2 when the Intermediate Range drawer OPERATION SELECTOR switch S201 is in the MSV LOCAL or MSV test positions (10-2%, 10%, or 102%).
The WR MSV valve is also available on the hand-held terminal screen 5 as a voltage scaled by the procedure volts.
The procedure GN IN converts the MSV GAIN adjust potentiometer R11 voltage to the equivalent gain factor GN MSV. The GN MSV value is available on the hand held terminal screen 4 and is set at full power levels to match calorimetric measurements.
Wide Range Power Splicing Calculations The wide range percent power output is derived in the procedure DATA IN which combines the wide range MSV signal WR MSV and the wide range CPS signal WR CPS to form a single output WR PR.
The procedure utilizes the dead-time corrected count rate CPS-G for determining the weighting of the WR CPS and WR MSV outputs. *The CPS related signal is used because in post accident conditions the MSV signal-can get hung-up due to high gamma fields. In comparison,.the CPS signal.is immune to gamma fields up to 106 R/hr with the factory discriminator setting of -1.00 volts. With the factory CPS GAIN setting of 1.00, the CPS and MSV signals overlap in the region of 50,000 to 500,000 CPS which corresponds to approximately 1 x
-3 to 1 x 10 2% MSV, respectively.
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(
PRINCIPLES OF OPERATION At count rates below 50,000 CPS (CPS G = 4.70), the wide range percent power output WR PR is.equal to the WR CPS value. At count rates above 500,000 CPS (CPS G = 5.70), the wide range percent power output WR PR is equal to the WR MSV value. An averaging technique is used to make smooth transitions as the count rate increases from the lower limit of 50,000 CPS to the upper limit of 500,000 CPS in the splicing range.
The D/A-1 converter output is always the wide range percent power output in all the Intermediate Range drawer OPERATION SELECTOR switch S201 positions. The D/A-2 converter'output is the wide range percent power output only when the Intermediate Range drawer OPERATION SELECTOR switch S201 is in the NORMAL position. The WR PR value is also avai.lable on the hand-held terminal screen 5 as percent.power level from 1.OOE-7% to 2.OOE+2% (10 to 200%) power..