ML22207A006
| ML22207A006 | |
| Person / Time | |
|---|---|
| Site: | SHINE Medical Technologies |
| Issue date: | 07/26/2022 |
| From: | Jim Costedio SHINE Medical Technologies |
| To: | Document Control Desk, Office of Nuclear Reactor Regulation |
| References | |
| 2022-SMT-0086 | |
| Download: ML22207A006 (6) | |
Text
3400 Innovation Ct
- Janesville, WI 53546
- 877.512.6554
- info@shinemed.com
- www.SHINEtechnologies.com July 26, 2022 2022-SMT-0086 10 CFR 50.30 U.S. Nuclear Regulatory Commission ATTN: Document Control Desk Washington, DC 20555
References:
(1)
SHINE Medical Technologies, LLC letter to the NRC, SHINE Medical Technologies, LLC Application for an Operating License, dated July 17, 2019 (ML19211C143)
SHINE Technologies, LLC Application for an Operating License Supplement No. 29 Pursuant to 10 CFR Part 50.30, SHINE Technologies, LLC (SHINE) submitted an application for an operating license for a medical isotope production facility to be located in Janesville, Wisconsin (Reference 1). SHINE has determined that a supplement to the operating license application is necessary to update the description of the highly integrated protection system (HIPS) programmable logic lifecycle process. provides the SHINE Final Safety Analysis Report (FSAR) Change Summary, including a mark-up of affected FSAR pages not previously submitted.
If you have any questions, please contact Mr. Jeff Bartelme, Director of Licensing, at 608/210-1735.
I declare under the penalty of perjury that the foregoing is true and correct.
Executed on July 26, 2022.
Very truly yours, James Costedio Vice President of Regulatory Affairs and Quality SHINE Technologies, LLC Docket No. 50-608 Enclosure cc:
Project Manager, USNRC SHINE General Counsel Supervisor, Radioactive Materials Program, Wisconsin Division of Public Health
Page 1 of 1 ENCLOSURE 1 SHINE TECHNOLOGIES, LLC SHINE TECHNOLOGIES, LLC APPLICATION FOR AN OPERATING LICENSE SUPPLEMENT NO. 29 FINAL SAFETY ANALYSIS REPORT CHANGE
SUMMARY
Summary Description of Changes FSAR Impacts Update to remove description of HIPS programmable logic lifecycle documents that have been incorporated into other programmable logic lifecycle documents.
Section 7.4, Figure 7.4-3 A markup of the Final Safety Analysis Report (FSAR) changes is provided as Attachment 1.
ENCLOSURE 1 ATTACHMENT 1 SHINE TECHNOLOGIES, LLC SHINE TECHNOLOGIES, LLC APPLICATION FOR AN OPERATING LICENSE SUPPLEMENT NO. 29 FINAL SAFETY ANALYSIS REPORT CHANGE
SUMMARY
FINAL SAFETY ANALYSIS REPORT MARKUP
Target Solution Vessel Chapter 7 - Instrumentation and Control Systems Reactivity Protection System SHINE Medical Technologies 7.4-48 Rev. 5 Planning documents for the implementation of the programmable logic lifecycle process are developed:
Project PLDP Project Configuration Management Plan Project V&V Plan Project Equipment Qualification Plan Project Test Plan Project Security Plan Project Integration Plan Planning phase documents are verified and processed in accordance with the vendor design document and data control procedures.
7.4.5.4.2.2 Requirements Phase A hardware requirements specification (HRS) is generated by the vendor to define the system hardware requirements detail. The HRS is generated in accordance with the vendor HRS development procedure.
A PLRS is generated to translate the conformed design specification into project-specific programmable logic requirements. The PLRS is generated in accordance with the vendor PLRS development procedure.
The PLRS is reviewed in accordance with the vendor verification process procedure.
Programmable logic lifecycle activities from this point forward are performed within an SDE using an IDN. Exceptions for the use of an SDE and IDN may be specified by management in accordance with contract requirements and/or regulatory requirements, as defined in the vendor SDE and IDN Security Plan.
The PLRS defines what the programmable logic should do, but not how the programmable logic meets the requirements. The complete description of the functions to be performed by the programmable logic is included in the PLRS.
When the programmable logic requirements are expressed by a requirement specification model, the model elements are categorized as either:
Model elements that represent programmable logic requirements including derived requirements, or Model elements that do not represent programmable logic requirements.
The requirement specification model is developed to define the programmable logic functionality in accordance with the vendor model-based development procedure and reviewed in accordance with the vendor verification process procedure.
7.4.5.4.2.3 Design Phase The input documents to the design phase are the SyRS, HRS, and PLRS.
Target Solution Vessel Chapter 7 - Instrumentation and Control Systems Reactivity Protection System SHINE Medical Technologies 7.4-49 Rev. 5 A hardware design specification is generated to define the system hardware requirements and design details. The hardware design specification is generated in accordance with the vendor hardware design specification development procedure.
A PLDS is generated to translate the PLRS into:
A description of the functional requirements A description of the system or component architecture A description of the control logic, data structures, input/output formats, interface descriptions, and algorithms The PLDS is generated in accordance with the vendor PLDS development procedure and reviewed in accordance with the vendor verification process procedure.
In the case when a PLDS is expressed by a design specification model, model elements that do not represent programmable logic requirements or architecture and are not input to a subsequent development activity may be included in a model (for example, comment elements). These elements will not be implemented in the executable code and therefore need to be clearly identified. Model elements are categorized as described in the vendor model-based development procedure as either:
Model elements that represent programmable logic design, including derived requirements or architecture, or Model elements that do not represent programmable logic design or architecture.
Design specification models are developed in accordance with the vendor model-based development procedure and are traceable, verifiable, and consistent.
Independent design review is performed to verify that the design meets the system requirements in accordance with the vendor verification process procedure. Design tests are performed to validate that the design meets the system requirements in accordance with the vendor test control procedure.
7.4.5.4.2.4 Implementation Phase The input documents to the implementation phase are the completed tasks and approved documents from the development phase. Although implementation phase activities may proceed, the outputs from the implementation phase are not approved until the development phase documents are approved.
The HIPS platform hardware and programmable logic components are integrated into the project during this phase to provide the target hardware and incorporate the HIPS platform programmable logic that has been previously designed, developed, tested, qualified, and implemented.
The implementation phase ends at the completion of the programmable logic design, development, and verification. Exit to the test phase occurs when the completed programmable logic is ready for validation on target hardware.
Chapter 7 - Instrumentation and Control Systems Target Solution Vessel Reactivity Protection System SHINE Medical Technologies 7.4-78 Rev. 5 Figure 7.4 TRPS and ESFAS Programmable Logic Lifecycle Process Project Configuration Management Plan Planning Phase Requirements Phase Design Phase Implementation Phase Test Phase Shipment and Installation Project Management Plan Design Review\\Release Design Review Checklist Application Specific Programmable Logic Requirements Specification Design Review\\Release Design Review Checklist System Requirements Specification Hazard Analysis Project Verification and Validation Plan Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist Test Plans Design Review\\Release Design Review Checklist Application Specific Programmable Logic Design Specification Design Review\\Release Design Review Checklist Test Plans Test Design Design Review\\Release Design Review Checklist Test Cases and Test Procedures Design Review\\Release Design Review Checklist Component Test Reports (Simulation)
Component Test Reports (Device)
Test Reports (System)
Integration Process Component Test Execution System Test Execution (FAT)
Project Quality Assurance Plan Design Review\\Release Design Review Checklist Audits & Reviews Audits & Reviews Audits & Reviews Audits & Reviews Audits & Reviews Source Code Generation Source Code Documentation Hardware Assembly Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist IV&V Final Report QA Report CM Report SAT Report (System)
Site Acceptance Test (SAT)
Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist Design Review\\Release Design Review Checklist V&V Design System Design Specification (As required based on PMP)
Hardware Design Specification Project Management QA Design Review\\Release Design Review Checklist Pre-developed HIPS Components Design Review\\Release Design Review Checklist HIPS Platform Hardware (HW) and Programmable Logic (PL)
Activities in the shaded area shall be performed within vendors Secure Development Environment (SDE) and Isolated Development Network (IDN)