Text

Reliability Report, Revision 5
	ML071770456
Person / Time
Site:	Wolf Creek
Issue date:	04/30/2007
From:	; Actel Corp
To:	; Office of Nuclear Reactor Regulation
References
	ET 07-0022
	Download: ML071770456 (52)
	v • d • e

Enclosure 5 to ET 07-0022 Actel Reliability Report

I4ctel Reliability Report Revision 5 April 2007

Accelerated Reliability Testing The failure rate of semiconductor devices is inherently small. For this reason Actel uses accelerated testing to assess reliability of its devices. Overstresses are used to produce the same failure mechanisms that would be seen under normal conditions but in a much shorter period of time. Acceleration factors are used by Actel to estimate failure rates based on the results of accelerated testing. The objective of this testing is to identify the failure mechanisms and eliminate them as a cause of failure during the useful life of Actel products.

Die selection is determined by both the largest die size and/or the currently available die. Actel will, whenever possible, test the largest die in a given family. Package selection for the testing is determined by test board availability and will not always include the largest package available. The primary use of this report is to include the reliability data of the silicon devices.

Actel Standard FIT Rate and MTTF Assumptions All of the FIT (Failure in Time) rate and MTTF (Mean Time to Failure) numbers reported here use a base set of assumptions. The given information in the summary tables and in the data tables allows other calculations for different variable values. Below are the basic variables used to calculate the results indicated in this report.

Activation energy (EA) = 0.7 eV, Junction temperature (Tj) = 55°C, and Confidence = 60%

Reliability testing (High Temperature Operating Life, or HTOL) of the devices are run either at 125°C or 150°C ambient and the maximum operating voltages reported in the datasheets. The results obtained by testing at ambient temperature 150 0C are converted to reflect at 125°C by using the Arrhenius equation for calculating the temperature acceleration factors and using their ratios.

The Acceleration Coefficient = a =Exp {(Ea/k) x (0/T 2 rT)}

Where:

Ea = Activation Energy (eV)

K = Boltzmann's constant (8.617 x 10-5 eV/OK)

T, = Temperature at accelerated conditions in degrees Kelvin T2 = Temperature at normal use conditions in degrees Kelvin This provides temperature acceleration factors. Assuming that the actual usage voltage is within the rated specification, acceleration coefficients are calculated for temperature stress. Sample sizes, total devices tested, device hours, and failures can be found in the data tables for each product family. The Arrhenius Life-Temperature relationship is widely used to model product life as a function of temperature. This relationship is used to express both a single failure mechanism's sensitivity to temperature and the product thermal acceleration factor.

General Note:

Notes at the end of each table correspond to the numbers or asterisk indicated by the superscript in the product column of that tables. If there is only one note, an asterisk is used. Failures indicated in parentheses represent false failures due to ESD or EOS.

2 Reliability Report Revision 5

9Acter Table of Contents Accelerated Reliability Testing ....................................................... 2 Actel Standard FIT Rate and MTTF Assumptions ..................................... 2 Reliability Sum m ary .............................................................. 4 ESD Perform ance ................................................................. 6 Group E Inspection-Generic Data (radiation hardness) .................................. 7 1.0 pm FPGA Reliability Summary .................................................... 8 1.0 pm FPGA (RH) Reliability Summary ............................................... 12 0.8 pm FPGA (RH) Reliability Summary ....................... ....................... 12 0.8 pm FPGA Reliability Summary ................................................... 13 0.6 pm FPGA Reliability Summary ................................................... 17 0.6 pm RTSX FPGA Reliability Summary .............................................. 21 0.45 pm FPGA Reliability Summary .................................................. 21 0.35 pm FPGA Reliability Summary .................................................. 23 0.25 pm MEC FPGA Reliability Summary ............................................. 25 0.25 pm Flash FPGA Reliability Summary ............................................. 27 0.25 pm UMC FPGA Reliability Summary ........................................... 29 Antifuse Reliability O verview ........................................................ 33 0.22 pm UMC FPGA Reliability Summary ............................................ 34 0.22 pm Flash FPGA Reliability Summary ......................................... 39 0.15 pm FPGA Reliability Summary ................................................. 41 0.13 pm Flash FPGA Reliability Summary ............................................. 44 List of C hanges ................................................................. 48 Reliability Report 3

Reliability Summary Table 1: Reliability Summary: FIT Rate by Device Technology Number of CMOS Device Device Technology Failures Hours Tj (0C) EA, eV Confidence FIT MTTF 1.0 pm CMOS FPGA 1 3.11E+08 55 0.7 60% 6.49 1.54E+08 1.0 pm CMOS FPGA (RHI020) 0 3.97E+07 55 0.7 60% 23.05 4.34E+07 0.8 pm CMOS FPGA (RH1280) 1 9.16E+07 55 0.7 60% 22.04 4.54E+07 0.8 pm CMOS FPGA 1 1.67E+08 55 0.7 60% 5.46 1.83E+08 0.6 pm CMOS FPGA 0 1.82E+08 55 0.7 60% 5.04 1.99E+08 0.6 pm RT54SX CMOS FPGA 0 2.29E+07 55 0.7 60% 39.88 2.51E+07 0.45 pm CMOS FPGA 0 6.96E+07 55 0.7 60% 13.16 7.60E+07 0.35 pm CMOs FPGA 0 6.31E+07 55 0.7 60% 14.51 6.89E+07 0.25 pm MEC CMOS FPGA 2 7.51E+07 55 0.7 60% 41.40 2.42E+07 0.25 pm Infineon Flash CMOS FPGA 0 3.62E+07 55 0.7 60% 25.30 3.95E+07 0.25 pm UMC CMOS FPGA 0 7.25E+08 55 0.7 60% 1.26 7.92E+08 0.22 pm UMC CMOS FPGA 0 4.99E+08 55 0.7 60% 1.83 5.45E+08 0.22 pm UMC Flash CMOS FPGA 0 4.92E+07 55 0.7 60% 18.59 5.38E+07 0.15 pm UMC CMOS FPGA 1 1.80E+08 55 0.7 60% 11.23 8.90E+07 0.13 pm Infineon Flash CMOS FPGA 0 1.19E+08 55 0.7 60% 7.67 1.30E+08 Note: Please referto "0.25pm UMC FPGA Reliability Summary" on page 29 for RTSX-SU antifuse FIT rate reliabilitydata 4 Reliability Report Revision 5

R4ctel Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family Numberof Device Technology and CMOS Product Family Failures Device Hours Tj (°C) EA, eV Confidence FIT MTTF 1.0 pm CMOS FPGA 1 3.11E+08 55 0.7 60% 6.49 1.54E+08 ACT1 1 1.60E+08 55 0.7 60% 13.72 7.29E+07 ACT2 0. 1.51E+08 55 0.7 60% 6.07 1.65E+08 1.0 pm CMOS FPGA (RHI020) 0 3.97E+07 55 0.7 60% 23.06 4.34E+07 0.8 jim CMOS FPGA (RH1280) 1 9.16E+07 55 0.7 60% 22.04 4.54E+07 0.8 pm CMOS FPGA (ACT3) 0 1.67E+08 55 0.7 60% 5.46 1 .83E+08 0.6 jim CMOS FPGA 0 1.82E+08 55 0.7 60% 5.04 1.99E+08 ACT3 0 6.13E+07 55 0.7 60% 14.93 6.70E+07 XL 0 7.73E+07 55 0.7 60% 11.83 8.45E÷07 DX 0 4.31E+07 55 0.7 60% 21.25 4.70E+07 0.6 pm RT54SX CMOS FPGA 0 2.29E+07 55 0.7 60% 39.88 2.51E+07 0.45 pm CMOS FPGA (MX) 0 6.96E+07 55 0.7 60% 13.16 7.60E+07 0.35 pm CMOS FPGA (SX) 0 6.31E+07 55 0.7 60% 14.51 6.89E+07 0.25 pm MEC CMOS FPGA 2 7.51E+07 55 0.7 60% 41.40 2.42E+07 SX-A 0 3.15E+07 55 0.7 60% 29.08 3.44E+07 RTSX-S 2 4.37E+07 55 0.7 60% 71.23 1.40E+07 0.25 jim Infineon Flash CMOS 0 3.62E+07 55 0.7 60% 25.30 3.95E+07 FPGA (ProASIC) 0.25 pm UMC CMOS FPGA 0 7.25E+08 55 0.7 60% 1.26 7.92E+08 (RTSX-SU) 0.22 pm UMC CMOS FPGA 0 4.99E+08 55 0.7 60% 1.83 5.45E+08 (SX-A/eX*)

0.22 pm UMC Flash CMOS FPGA 0 4.92E+07 55 0.7 60% 18.59 5.38E+07 (ProASICPu) 0.15Mm UMC CMOS FPGA 0 2.67E+07 55 0.7 60% 34.23 2.92E+07 (Axcelerator) 0.15 pm UMC CMOS FPGA 1 1.53E+08 55 0.7 60% 13.19 7.58E+07 (RTAX-S) 0.13 pm Infineon Flash CMOS 0 1.19E+08 55 0.7 60% 7.67 1.30E+08 FPGA (ProASIC3)

Note: *The eX family of devices is covered underthe 0.22 pm FPGA family by similarity (extension). Testing is conducted on the SX-A devices for the eX family. The smallest SX-A device (A54SXO8A) is the largestdie equivalent to the eX256.

Reliability Report Revision 5 5

I ESD Performance Table 3: Summary of ESD Performance for All Actel Product Families ESD (volts)

Product Family HBM Family Members Fab Technology ACT1 2000 A1010B, A1020B 1.0 pm ACT2 1000 A1225A, A1240A, A1280A, RT1280A 1.0 pm RHI020 4100 RH1020, RT1020 1.0 pm RH1280 1500 RH1280 0.8 pm ACT3 2000 A1415A, A1425A, A1460A, A14100A. &RT Variants 0.8 pm XL 1500 A1225XL,A1240XLA1280XL 0.6 pm DX 2000 A3265DX, A32100DX, A32140DX, A32200DX, A32300DX 0.6 pm RT54SX 2000 RT54SX16, RT54SX32 0.6 pm MX 2000 A40MX02, A40MX04,A42MX09, A42MX16, A42MX24, A42MX36 0.45 pm SX 2000 A54SX08, A54SX16, A54SX16P, A54SX32 0.35 pm SX-A 75* A54SX16A, A54SX32A, A54SX72A 0.25 pm RTSX-S 75* RT54SX32S, RT54SX72S 0.25 pm ProASIC 2000 A50OK050, A50OK130, A500K180, A500K270 0.25 pm RTSX-SU 75* RT54SX32SU, RT54SX72SU 0.25 pm SX-A 75* A54SX08A, A54SX16A, A54SX32A, A54SX72A 0.22 pm eX 50" eX64,eX128,eX256 0.22 pIm ProASICELus 2000 APA075, APA150, APA300, APA450, APA600, APA750, APA1000 0.22 pm Axcelerator 2000 AX125, AX250, AX500, AX1000, AX2000 0.15 pm RTAX-S 2000 RTAX250S, RTAX1000S, RTAX2000S 0.15 pm ProASIC3 2000 A3P030, A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000 0.13 pm Note: *ESD tests were performed on all pins. All but four pins show ESD performance of Z,000 volts, HBM. Refer to the Electro-Static Dischargeapplicationnote at http://www.actel.conidocumentsIESDAN.pdffor more details.

6 Reliability Report Revision 5

4ctelI Group E Inspection-Generic Data (radiation hardness)

Verification of radiation performance for each wafer lot is performed through in-line parameter monitoring in the QML RHA wafer production line. Table 4 lists the summarized radiation performance of RH FPGAs.

Table 4: Radiation Performance for RadHard Devices (data published on SMDs)

Total Dose RH1280 RH102O Units TID Total Ionizing Radiation Dose 300 300 krads (Si)

SEP (Single Event Phenomena)

SEL Single Event Latch-Up 177 >84 LETth (MeV-cm2/mg)

Single Event Upset- Combinatorial 17 >8 LETth (MeV-cm2/mg)

SEUI Single Event Upset - Sequential 4 - LETth (MeV-cm2/mg)

SEDR Single Event Dielectric Rupture >60 >40 LETth (MeV-cm21mg)

Note: Wafer Lot Acceptance (SEM)-RHCMOS4EF (ONO PBEOL) wafer process utilizes plugged vias, which eliminates the step coverage issue, so the SEM metallization inspection is not required.

Reliability Report Revision 5 7

1.0 pm FPGA Reliability Summary Table 5: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours AI010B PLCC68 U1G-01 79 1000 0 0 0 79000 A1010B PLCC68 U1G-02 57 500 0 0 - 28500 A1010B PQFP100 U9G01P 76 1000 0 0 0 76000 A10200 CQFP84 UP121 24 1000 0 0 0 24000 A1020B PGA84 U1P057/0014 97 2000 0 0 0 0 194000 A1020B PGA84 JJ-13 30 1000 0 0 0 30000 A1020B PGA84 JJ-13 80 500 0 0 40000 A10208 PLCC84 JJ-14 45 1000 0 0 0 45000 A10208 PLCC84 JJ-15 45 1000 0 0 0 45000 A1020B PLCC84 JJ-17 45 1000 0 0 0 45000 A1020B PLCC84 JJ-16 80 1000 0 0 0 80000 A1020B PLCC84 U1P-01 40 1000 0 0 0 40000 A1020B PLCC84 U1P-02 40 1000 0 0 0 40000 A1020B PLCC84 JJ-24 87 1000 0 0 0 87000 A1020B PLCC84 EBFJOOI 40 1000 0 0 0 40000 A1020B PLCC84 EBFI004 40 1000 0 0 0 40000 A1020B PLCC84 U1P209B 40 1000 0 0 0 40000 A1020B PLCC84 U9P-004 47 1000 0 0 0 47000 A1020B PLCC84 U9P046 100 1000 0 0 0 100000 A1020B PLCC84 6085878 100 1000 0 0 0 100000 A1020B PLCC84 U9P128 100 1000 0 0 0 100000 A1020B PLCC84 UB9P034 98 2000 0 0 0 0 196000 A1020B PQFP100 U1P41HM 80 1000 0 0 0 80000 A1020B PQFP100 U1P05 129 1000 0 0 0 129000 A1020B1 PGA84B UBIPO01 77 615 0 0 0 47355 A1020B 2 PQFP100 U9P01, 133 1000 0 1 0 133000 U9P021A A1020B VQFP80 U1P25 45 500 0 0 - 22500 A1020B VQFP80 U1P83 43 1000 0 0 0 43000 A1020B VQFP80 U1P25 39 1000 0 0 0 39000 1 77 615 0 0 0 47355 A1020B PGA84B UB1P008 A1225A PGA100 UJ-01 80 1000 0 0 0 80000 Notes:

1. Tested at 1500C. Equivalent hours correspondingto 1250C were used to calculate the FIT rates.

2. Functional failure was observed for the product A 1020B, run U9PO1, at 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months . No defects were observed after decapsulation.

8 Reliability Report Revision 5

!ActelI Table 5: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A1225A PQFP100 MIX 32 1000 0 0 0 32000 A1225A PQFP100 UJ-01 127 1000 0 0 0 127000 A1225A PQFP100 U1J-02 80 1000 0 0 0 80000 A1240A PGA132 T13257 7 500 0 0 - 3500 A1240A PGA132 UI-01 50 1000 0 0 0 50000 A1240A PLCC84 UI-03 80 1000 0 0 .0 80000 A1240A PLCC84 E-04 30 2000 0 0 0 0 60000 A1240A PQFP144 MIX 36 1000 0 0 0 36000 A1240A PQFP144 E-02,03 100 1000 0 0 0 100000 A1240A PQFP144 U11-26 80 1000 0 0 0 80000 A1280A CQFP172 U1H486 81 1000 0 0 0 81000 A1280Al - CQFP172 UBIH001 77 615 0 0 47355 A1280A CQFP172 U1H486 81 1000 0 0 0 81000 A1280A1 CQFP172 U1H442 81 615 0 0 49815 A1280A PQFP160 ADC18X 130 1000 0 0 0 130000 A1280A PQFP160 EBFJO02 30 168 0 5040 A1280A PQFP160 EBFJO03 30 168 0 5040 A1280A PQFP160 EBFJO04 20 168 0 3360 A1280A PQFP160 UIH-01 27 2000 0 0 0 0 54000 A1280A PQFP160 U1H-02 27 2000 0 0 0 0 54000 A1280A PQFP160 UIH-18 80 1000 0 0 0 80000 RT1280AI CQFP172 U1H611 15 615 0 0 9225 TOTAL Units for 1.0 pm FPGA = 4050 Total Test Time Hours = 3990396 TOTAL Failures for 1.0 pm FPGA = I ACT1 TOTAL Units for 1.0 pm FPGA = 2013 Total Test Time Hours = 2057710 TOTAL Failures for 1.0 pm ACTI FPGA = 1 ACT2 TOTAL Units for 1.0 pm FPGA = 2037 Total Test Time Hours = 1932686 TOTAL Failures for 1.0 pm ACT2 FPGA = 0 Notes:

1. Tested at 1500C. Equivalent hours corresponding to 1250C were used to calculate the FIT rates.

2. Functional failure was observed for the product A 1020B, run U9PO1, at 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months . No defects were observed after decapsulation.

Reliability Report Revision 5 9

Table 6: 859C/85% Temperature Humidity BIAS Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A1020B PLCC84 JJ-14 27 1000 0 0 0 27000 A1020B PLCC84 JJ-15 27 1000 0 0 0 27000 A1020B PLCC84 JJ-17 27 1000 0 0 0 27000 TOTAL Units for 1.0 lim FPGA = 81 Total Test Time Hours = 81000 TOTAL Failures for 1.0 pm FPGA = 0 Table 7: Biased Humidity (HAST)

Test HourslFailures Date Number Unit Product Package Wafer Lot Code of Units Test Time 50 100 200 250 Hours A1020B PLCC84 EBFJO01 44 100 0 0 ,4400 A1O20B PLCC84 EBF1004 36 100 0 0 3600 A1020B PLCC84 U9PO1 29 100 0 0 2900 A1020B PLCC84 U9P021A 50 100 0 0 5000 A1020B PLCC84 U9P039 50 100 0 0 5000 A1O20B PLCC84 U9P046 50 100 0 0 5000 A1020B PLCC84 6085878 50 100 0 0 5000 A1020B PLCC84 103501 61 100 0 0 6100 TOTAL Units for 1.0 lm FPGA = 370 Total Test Time Hours = 37000 TOTAL Failures for 1.0 Mm FPGA = 0 10 Reliability Report Revision 5

MActer Table 8: Temperature Cycle Number of Cycles/Failures Date Number Test Product Package Wafer Lot Code of Units Cycles 100 500 1000 2000 Cycles (0°C - +125°C)

TOTAL Units for 1.0 pm FPGA = 0 Total Test Cycles 0 TOTAL Failures for 1.0 pm FPGA = 0 (01C - +125°C)

(-55°C - +125°C)

A1020B PLCC68 1U9P186 30 1000 0 0 3 0 30000 A1020B PQFP100 U9G042 25 1000 0 sC 25000 TOTAL Units for 1.0 pm FPGA 55 Total Test Cycles 55000 TOTAL Failures for 1.0 pm FPGA = 0 (-55°C - +125°C)

(-65°C - +150'C)

A1010B PLCC68 UIG-01,02 40 1000 0 0 0 40000 A1020B PLCC84 JJ14-17 81 1000 0 0 0 81000 A1020B PLCC84 U1P-01,02 40 1000 0 0 0 40000 A1020B PLCC84 EBFJO01 80 1000 0 0 0 80000 A1020B PQFP100 U1P41HM 80 1000 0 0 0 80000 A1020B PLCC84 EWAI003 80 1000 0 0 0 80000 A1020B PLCC84 U1P-209B 15 1000 0 0 0 15000 A1020B PQFP100 U1P05 80 1000 0 0 0 80000 A1020B PLCC84 U9P021A 55 1000 0 0 0 55000 A1020B PLCC84 U9P01 23 1000 0 0 0 23000 A1020B PLCC84 U9P039 50 1000 0 0 0 50000 A1020B PLCC84 U9P046 50 1000 0 0 0+ 50000 A1020B PLCC84 6085878 50 1000 0 0 0 50000 A1020B PLCC84 103501 62 1000 0 0 0 62000 TOTAL Units for 1.0 pm FPGA = 786 Total Test Cycles 786000 TOTAL Failures for 1.0 pm FPGA = 0 (-65*C - +150°C)

Table 9: Pressure Pot (Unbiased Autoclave)

Test HourslFailures Date Number Unit Product Package Wafer Lot Code of Units Test Time 96 168 240 336 Hours A1010B PLCC68 U1G-01 40 264 0 0 0 10560 A1020B PLCC84 JJ14-17 81 264 0 0 0 21384 A1020B PLCC84 U1P-01 40 264 0 0 0 10560 A1020B PLCC84 U09039 50 264 0 0 0 13200 TOTAL Units for 1.0 pm FPGA = 211 Total Test Time Hours = 55704 TOTAL Failures for 1.0 pm FPGA = 0 Reliability Report Revision 5 11

I 1.0 pm FPGA (RH) Reliability Summary Table 10: High Temperature Operating Life (HTOL) 1 Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours RH1020 CQFP172 T8036 78 1000 0 0 0 78000 RH1020 CQFP172 T9064 40 1000 0 0 0 40000 2 15 615 0 0 9225 RH1020 CQFP172 T9085 RH1020 CQFP172 T9089 8 1000 0 0 0 8000 RH1020 CQFP172 T2208 18 1000 0 0 0 18000 3 1000 0 0 0 48000 RH1020 CQFP172 T2404 48 TOTAL Units for 1.0 pm RHI020 FPGA = 207 5615 Total Test Time Hours = 201225 TOTAL Failures for 1.0 pm RH1020 FPGA 0 Notes:

1. Data from BAe

2. Tested at 1500C. Equivalenthours correspondingto 1250C were used to calculate the FIT rates.

3. One unit failed at -550C after completing 1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months , which was verified to be false failure due to tester noise.

0.8 pm FPGA (RH) Reliability Summary Table 11: High Temperature Operating Life (HTOL) 1 Test HourslFailures Number Test Unit Product Package Wafer Lot Date Code Units Time 168 500 1000 2000 Hours RH1280 CQFP172 FPGAQQC11 95507A.1 6 1000 0 0 0 6000 RH1280 CQFP172 FPGAQQC11 95507C.1 17 1000 0 0 0 17000 RH1280 CQFP172 FPGAQQCI1 95506C.1,2,3 34 1000 0 0 0 34000 RH1280 CQFP172 FPGAQQC11 95506D.1 20 1000 0 0 0 20000 RH1280 CQFP172 T7013C 12 1000 0 0 0 12000 RH1280 CQFP172 T7013C 96580C.1 33 1000 0 0 0 33000 2 1000 1 0 0 32000 RH1280 CQFP172 T7013C 96580E.1 32 RH1280 CQFP172 T9065 1990510 & 61 1000 0 0 0 61000 1990511 RH1280 CQFP172 T9066 10 1000 0 0 0 10000 RH 1280 CQFP172 T9072 12 1000 0 0 0 12000 RH1280 CQFP172 T9088- 38 1000 0 0 0 38000 RH1280 CQFP172 T2208 59 1000 0 0 0 59000 TOTAL Units for 1.0 pm RH1280 FPGA = 334 12000 Total Test Time Hours = 334000 TOTAL Failures for 1.0 pm RH1280 FPGA I Notes:

1. Data from BAe

2. No defect found. Part destroyedin analysis.

'12 Reliability Report Revision 5

MActer 0.8 pm FPGA Reliability Summary Table 12: High Temperature Operating Life (HTOL)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours 1 47355 A14100A CQFP256 UBCLP01A 77 615 0 0 0 1 0 0 50430 A14100A CQFP256 UCL058 82 615 0 1 2 0 0 47970 A14100A . CQFP256 UCL072 78 615 (1) 3 15000 A14100A CQFP256 UCL049 15 1,000 0 0 (1)

A14100A COFP256 UCL055 18 1,000 0 0 0 18000 1 46002 A14100A CQFP256 UCL058 82 561 0 A14100A CQFP256 UCL073 10 1,000 0 0 0 10000 1 16700 A14100A CQFP256 UCL082 10 1,670 0 0 0 A14100A PBGA313 25290820 45 1000 0 0 0 45000 A14100A RQFP208 24239130 51 1000 0 0 0 51000 A14100A RQFP208 UCLO1 25 1000 0 0 0 25000 1 0 79950 A1425A PGA133 UCJO1/02E/03 130 615 0 0 A1425A PGA133 JK08.09,10 140 1000 0 0 0 140000 A1425A PGA133 ACN32804, 130 1000 0 0 0 130000 ACN30805, ACN33807 A1425A1 PGA133 UCJ01, 2,3 130 615 0 0 0 79950 A1425A PLCC84 JK08, 09, 10 135 1000 0 0 0 135000 A1425A PQFP100 UCJ013 100 1000 0 0 0 100000 A1440A VQFPIOO 51940 79 1000 0 0 0 79000 A1440A VQFP100 JN05 79 1000 0 0 0 79000 A1460A1 PGA207 UCK056 80 561 0 44880 1

A1460A CPGA207 UCKT01 81 561 0 45441 1

A1460A PGA207 UCK005 77 615 0 0 0 47355 1 49200 A1460A PGA207 UCK056 80 615 0 0 1 49815 A1460A PGA207 UCKT01 81 615 0 0 A1460A PGA207 JL-01 80 1000 0 0 0 80000 A1460A PGA207 JL-06B 65 1000 0 0 0 65000 Notes:

1. Tested at 1500C. Equivalent hours corresponding to 1250 C were used to calculate the FIT rates.

2. ProductA14100A, run UCLO72, at 168 hours0.00194 days 0.0467 hours 2.777778e-4 weeks 6.3924e-5 months , one unit failed gross-functional. FA shown contact spike caused by ESD/

EOS, qualificationpassed by TRB approval.

3. ProductA14100A, run UCLO49, at 1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months , unit failed was proven by FA as EOS. No functional failures observed.

Reliability Report Revision 5 13

Table 12: High Temperature Operating Life (HTOL) (Continued)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A1460A PGA207 PC435091, PC435092, 80 1000 0 0 0 80000 PC435093 A1460A PQFP208 20072420 0026 30 1000 0 0 0 30000 A1460A PQFP208 20094560 0022 29 1000 0 0 0 29000 A1460A PQFP208 20145270 0026 30 1000 0 0 0 30000 A1460A PQFP208 29350050 9947 65 2000 0 0 0 0 130000 A1460A PQFP208 UCK070 9946 22 2000 0 0 0 0 44000 A1460A PQFP208 JL-01 80 1000 0 0 0 80000 A1460A PQFP208 JL-03 62 1000 0 0 0 62000 RT14100A CQFP256 UCLO55 18 1000 0 0 0 18000 RT14100A CQFP256 UCL073 9949 15 1000 0 0 0 15000 RT14100A CQFP256 UCL073 0019 10 1000 0 0 0 10000 1 43197 RT14100A CQFP256 UCL72 9931 77 561 0 9925 TOTAL Units for 0.8 pm FPGA = 2478 Total Test lime Hours = 2148245 TOTAL Failures for 0.8 pm FPGA = 0 TOTAL Units for 0.8 pm ACT3 FPGA =1 2478 1 1 Total Test Time Hours = 2148245 TOTAL Failures for 0.8 pm ACT3 FPGA 0 Notes:

1. Tested at 1500C. Equivalenthours corresponding to 1250C were used to calculate the FIT rates.

2, ProductA14100A, run UCLO72, at 168 hours0.00194 days 0.0467 hours 2.777778e-4 weeks 6.3924e-5 months , one unit failedgross-functional. FA shown contact spike caused by ESD/

EOS, qualificationpassedby TRB approval.

3. ProductA 14100A, run UCLO49, at 1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months , unit failed was proven by FA as EOS. No functional failures observed.

Table 13: 85°CI85%Temperature Humidity Bias Test HourslFailures Date Number of Test Product Package Wafer Lot Code Units Time 168 500 1000 .2000 Unit Hours A14100A PBGA313 25290820 45 1000 0 0 0 45000 TOTAL Units for 0.8 pm FPGA = 45 Total Test Time Hours = 45000 TOTAL Failures for 0.8 pm FPGA = 0 14 Reliability Report Revision 5

IActeI Table 14: Biased Humidity (HAST)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours A1425A PLCC84 JK8,9,10 81 100 0 0 8100 A1425A PQFP100 ACN32804, 80 .100 0 0 8000 ACN30805, ACN33807 A1425A PQFP100 UCJ01,2,3 80 100 0 0 8000 A1440A VQFP100 JN05 45 100 0 0 4500 A1440A VQFP100 51940 45 100 0 0 4500 A1460A PQFP208 .JL04A 80 100 0 0 8000 A1460A PQFP208 WB24279010 47 100 0 0 4700 A14100A RQFP208 24239130 14 100 0 0 1400 TOTAL Units for 0.8 gjm FPGA 472 Total Test Time Hours = 47200 TOTAL Failures for 0.8 pm FPGA 0 Reliability Report Revision 5 15

Table 15: Temperature Cycle I_ _ _ I I Number of Cycles/Failures Product Package Wafer Lot Date Code Number of Units TestI Cycles 1 100 200 1 500 I 1000 I Cycles 0

(-65-C - +I5M )

A14100A PBGA313 25290820 78 500 0 0 0 39000 A14100A RQC208 MIX 24 100 0 2400 A14100A RQC209 MIX 24 100 0 2400 A14100A RQFP208 24239130 14 500 0 0 0 7000 A14100A RQFP208 UCLO1 31 500 0 0 0 15500 A14100A RQFP208 2537198 19 100 0 1900 A1425A PGA133 JK8,9,10 81 500 0 0 0 40500 A1425A PLCC84 JK8,9,10 83 500 0 .0 0 41500 A1425A PQFP100 UCJ01,2,3 80 500 0 0 0 40000 A1425A PQFP100 ACN32804, 80 500 0 0 0 40000 ACN30805, ACN33807 A1440A PQFP160 JN-02 80 500 0 0 0 40000 A1440A VQFP100 JN-05 80 500 0 0 1 40000 A1440A VQFP100 51940 45 500 0 0 0 22500 A1460A PGA207 JL-01 80 500 0 0 0 40000 A1460A PGA207 PC435091, 80 500 0 0 0 40000 PC435092, PC435093 A1460A PQFP208 JL-01 80 500 0 0 0 40000 A1460A PQFP208 25364430 45 500 0 0 0 22500 A1460A PQFP208 2610001 80 500 0 0 0 40000 TOTAL Units for 0.8 pm FPGA = 1084 Total Test Cycles 515200 TOTAL Failures for 0.8 pm FPGA = I Table 16: Pressure Pot (Unbiased Autoclave)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 48 96 168 336 Hours A14100A PBGA313 25290820 45 96 0 0 4320 TOTAL Units for 0.8 pm FPGA = 45 Total Test Time Hours = 4320 TOTAL Failures for 0.8 pm FPGA = 0 16 Reliability Report Revision 5

SActel 0.6 pm FPGA Reliability Summary Table 17: High Temperature Operating Life (HTOL)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A1225XL PQFP100 ACP02187.1 26 1000 0 0 0 - 26000 A1225XL PQFP100 ACQ10102 56 1000 0 0 0 - 56000 A1240XL PLCC84 ACP57584.1 100 1000 0 0 0 - 100000 A1240XL PQFP144 MIX 56 1000 0 0 0 - 56000 A1240XL PQFP144 ACR50594.1 228 168 0 38304 A1240XL PQFP144 ACR50594.1 143 168 0 24024 A1240XL PQFP144 ACRS0594.1 227 168 0 38136 A1240XL PQFP144 ACP01117.1, 52 1000 0 0 0 - 52000 ACN51939.1 A1280XL' CQFP172 ACT10293.1 80 561 0 0 44880 A1280XL1 CQFP172 ACT10293.1 80 615 0 0 49200 1

A1280XL CQFP172 ACY953401 77 615 0 0 47355 2

A1280XL', PGA176 ACU413553 77 615 (1) 0 47355 A1280XL1 PGA176 ACV715861 77 561 0 0 43197 A1280XL PLCC84 MIX 100 1000 0 0 0 100000 A1280XL PQFP160 ACR53214 129 168 0 21672 A1280XL PQFP160 ACU458071/ 0008 86 2000 0 0 0 0 172000 A1280XL PQFP160 ACP212072, 76 1000 0 0 0 76000 ACP19329.1 A14100BP RQFP208 26026670 27 1000 0 0 0 27000 A1415A PQFP100 ACP17300 100 1000 0 0 0 100000 A1425A PGA133 UCJ01,02,03 130 1670 0 0 0 217100 A1425A PQFP100 ACP17300 101 2000 0 0 0 0 202000 A1425A PQFP100 ACP122761 100 1000 0 0 0 100000 A1425A PQFP100 ACP12285 88 1000 0 0 0 88000 A1460BP PQFP208 25430540 52 1000 0 0 0 52000 1 49200 A32100DX CQFP84 ACR50293.1 80 615 0 0 A32140DX PQFP208 ACP562551 28 2000 0 0 0 0 56000 Notes:

1. Tested at 1500C. Equivalent hours corresponding to 1250C were used to calculate the FIT rates.

2. ProductA1280XL, run 2ACU413553, at 160 hours0.00185 days 0.0444 hours 2.645503e-4 weeks 6.088e-5 months ; unit failed was verified to be ESOIEOS.

3. Product A32200DX, run ACT16685.1, at 160 hours0.00185 days 0.0444 hours 2.645503e-4 weeks 6.088e-5 months , rejects are due to electrical over stress (EOS) or ESD), which are induced by HP1 tester during the same time frame in which these devices are tested. Failure modes are not life-test induced; therefore, the qualificationis still passed.

Reliability Report Revision 5 17

-I Table 17: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A32140DX PQFP208 G10854 26 1000 0 0 0 26000 A32140DX PQFP160 ACP540231 26 1000 0 0 0 26000 A32140DX PQFP160 25464510 26 1000 0 0 0 26000 A32140DX PQFP208 ACP33277.1 75 1000 0 0 0 75000 A32140DX PQFP208 ACP56255.1 52 1000 0 0 0 52000 A32200DX 1 ,3 CQFP256 ACT16685.1 77 1000 (1) 0 0 77000 A32200DX CQFP256 ACV648421 5 615 0 0 3075 1 5 615 0 0 3075 A32200DX CQFP256 ACV648421 1 29 1000 0 0 0 29000 A32200DX PQFP208 26207340 A32300DX RQFP240 ACQ09069.1 26 2000 0 0 0 0 52000 A3265DX PQFP160 ACP163684 78 1000 0 0 0 78000 TOTAL Units for 0.6 pm FPGA = 2801 Total Test Time Hours 2330573 TOTAL Failures for 0.6 pm FPGA = 0 ACT3 TOTAL Units for ACT3 FPGA = 598 Total Test Time Hours = 786100 TOTAL Failures for ACT3 FPGA = 0 XL TOTAL Units for XL FPGA = 1670 Total Test Time Hours = 992123 TOTAL Failures for XL FPGA = 0 DX TOTAL Units for DX FPGA = 1207 Total Test Time Hours = 552350 TOTAL Failures for DX FPGA = 0 Notes:

0 0

1. Tested at 150 C. Equivalent hours correspondingto 125 C were used to calculate the FIT rates.

2. ProductA 1280XL, run 2ACU413553, at 160 hours0.00185 days 0.0444 hours 2.645503e-4 weeks 6.088e-5 months ; unit failed was verified to be ESD/EOS.

3. Product A32200DX, run ACT16685. 1, at 160 hours0.00185 days 0.0444 hours 2.645503e-4 weeks 6.088e-5 months , rejects are due to electricalover stress (EOS) or ESD), which are induced by HP1 tester during the same time frame in which these devices are tested. Failure modes are not life-test induced; therefore, the qualification is still passed.

18 Reliability Report Revision 5

MActelI Table 18: Biased Humidity (HAST)

Test Hours/Failures Date Number Unit Product Package Wafer Lot Code of Units Test Time 50 100 200 250 Hours A1225XI PQFP100 ACP02187.1 17 100 0 0 1700 A1240XL PQFP144 ACP01117.1. 31 100 0 0 3100 ACN51939.1 A1280XL PQFP160 ACP19329.1 76 100 0 0 7600 ACP212072 A1280XL PQFP160 ACP33235.1 76 100 0 0 7600 A1280XL PQFP160 ACQ01769 40 100 0 0 4000 A1280XL PQFP160 ACQ05561 39 100 0 0 3900 A3265DX PQFP160 ACP163684 40 100 0 0 4000 A1415A PQFP100 ACP17300 50 100 0 0 5000 A1425A PQFP100 ACP122761 50 100 0 0 5000 A32140DX PQFP160 ACP54023.1 26 100 0 0 2600 A32140DX PQFP208 ACP33277.1, 76 100 0 0 7600 ACP55730.1, ACP54023.1 A32200DX PQFP208 26207340 26 100 0 0 2600 A14100BP RQFP208 26330340 26 100 0 0 2600 A32200DX PQFP208 ACQ03818.1 30 100 0 0 3000 A1280XL PQFP160 26084380 58 100 0 0 5800 A32140DX PQFP208 55558 25 100 0 0 2500 TOTAL Units for 0.6 ljm FPGA = 686 Total Test Time Hours 68600 TOTAL Failures for 0.6 PIm FPGA 0 Reliability Report Revision 5 19

Table 19: Temperature Cycle Number of CycleslFailures Date Number Test Product Package Wafer Lot Code of Units Cycles 100 200 500 1000 Cycles A1280XL TQFP176 25026540 17 500 0 0 0 8500 A1280XL PQFP160 25312500, 25312480 76 500 0 0 0 38000 A1280XL PQFP160 25312500,25312480 76 200 0 0 15200 A1280XL PQFP160 25312500, 25312480 75 500 0 0 0 37500 A1280XL PQFP160 25312500, 25312480 75 500 0 0 0 37500 A1280XL PQFP160 25312500, 25312480 74 500 0 0 0 37000 A1280XL PQFP160 25312500, 25312480 76 500 0 0 0 38000 A1280XL PQFP160 25504560 36 500 0 0 0 18000 A1425A PGA133 JK8,9,10 81 500 0 0 0 40500 A1425A PLCC84 JK8,9,10 83 500 0 0 0 41500 A1425A PQFP100 UCJ01,2,3 80 500 0 0 0 40000 A1425A PQFP100 ACN32804, ACN30805, 80 500 0 0 0 40000 ACN33807 A1440A PQFP160 JN-02 80 500 0 0 0 40000 A1440A VQFP100 JN-05 80 500 0 0 1 40000 A1440A VQFP100 51940 45 500 0 0 0 22500 A1460A PQFP208 JL-01 80 500 0 0 0 40000 A1460A PGA207 JL-01 80 500 0 0 0 40000 A1460A PGA207 PC435091, PC435092, 80 500 0 0 0 40000 PC435093 A1460A PQFP208 25364430 45 500 0 0 0 22500 A1460A PQFP208 2610001 80 500 0 0 0 40000 A14100A RQFP208 24239130 14 500 0 0 0 7000 A14100A RQFP208 UCLO0 31 500 0 0 0 15500 A14100A RQFP208 2537198 19 100 0 1900 A14100A PBGA313 25290820 78 500 0 0 0 39000 A14100A RQFP208 MIX 24 100 0 2400 A14100A RQFP208 MIX 24 100 0 2400 TOTAL Units for 0.6 pm FPGA = 1589 Total Test Cycles 744900 TOTAL Failures for 0.6 pm FPGA = 1 Table 20: Pressure Pot (Unbiased Autoclave)

Test Hours/Failures Date Number Product Package Wafer Lot Code of Units Test Time 48 96 168 336 Unit Hours A1280XL TQFP176 25312480 45 168 0 0 0 7560 A14100A PBGA313 25290820 45 96 0 0 4320 TOTAL Units for 0.6 pm FPGA = 90 Total Test Time Hours 11880 TOTAL Failures for 0.6 pm FPGA = 0 20 Reliability Report Revision 5

4ctel" 0.6 pm RTSX FPGA Reliability Summary Table 21: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours RT54SX16* CQFP256 P05 77 615 0 0 47355 RT54SX16 CQFP256 P04 9931 46 2000 0 0 0 0 92000 RT54SX16 PQFP208 P02, P03, P04 81 1000 0 0 0 81000 RT54SX16 CQFP256 T6HP12 101 240 0 24240 RT54SX32* CQFP208 T6JP01A 76 615 0 0 46740 RT54SX32* CQFP256 T6JP05A 5 615 0 0 3075 TOTAL Units for 0.6 pm RTSX FPGA = 386 Total Test Time Hours = 294410 TOTAL Failures for RTSX 0.6 tpm FPGA = 0 Note:

Tested at 1500C. Equivalent hours correspondingto 1250C were used to calculate the FITrates.

0.45 pm FPGA Reliability Summary Table 22: High Temperature Operating Life (HTOL)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A40MX04 PLCC84 2ACR23038.3 30 2000 0 0 0 0 60000 A40MX04 PLCC84 2ACR23038.3 45 2000 0 0 0 0 90000 A40MX04 PLCC84 2ACT160021 77 2000 0 0 0 0 154000 A40MX04 PLCC84 2ACU040091 77 2000 0 0 0 0 154000 (DC9919)

A40MX04 PLCC84 2XZR24206.5 29 2000 0 0 0 0 58000 A42MX16 PLCC84 2ACU492561 148 1000 0 0 0 148000 (DC0012)

A42MX16 PQFP160 2XZR25104.1 26 2000 0 0 0 0 52000 1

A42MX36 CQFP208 2ACZ310131 77 615 0 0 0 47355 12 A42MX36 , CQFP256 2ACT363611 77 615 (1) 0 47355 A42MX36 PQFP208 2ACT10221 27 2000 0 0 0 0 54000 1

A42MX36 CQFP208 2ACU523241 0019 45 615 0 0 0 27675 TOTAL Units for 0.45 ljm FPGA = 658 Total TestTime Hours = 892385 TOTAL Failures for 0.45 pim FPGA = 0 Notes:

1. Tested at 1500C. Equivalent hours corresponding to 1250C were used to calculate the FIT rates.

2. Product A42MX36, run 2ACT36361 1, at 168 hours0.00194 days 0.0467 hours 2.777778e-4 weeks 6.3924e-5 months , unit failed was verified to be ESDIEOS.

Reliability Report Revision 5 21

Table 23: Biased Humidity (HAST)

Test Hours/Failures Date Number Unit Product Package Wafer Lot Code of Units Test Time 50 100 200 250 Hours A40MX04 PLCC84 2ACR23038.3 81 100 0 0 8100 A40MX04 PLCC84 2ACR23039.1 25 100 0 0 2500 A42MX09 PQFP160 2ACT110181 30 100 0 0 3000 A42MX16 PQFP160 2XZR25104.1 25 100 0 0 2500 A42MX36 BGA272 2ACT180141 76 100 0 0 7600 A42MX36 PQFP208 2ACT110221 27 50 0 1350 TOTAL Units for 0.45 prm FPGA = 264 Total Test Time Hours = 25050 TOTAL Failures for 0.45 prm FPGA = 0 Table 24: Unbiased Humidity Test Hours/Failures Date Number Unit Product Package Wafer Lot Code of Units Test Time 50 100 200 250 Hours A42MX09 PQFP160 2ACT052662 9817 30 100 0 0 3000 TOTAL Units for 0.45 pm FPGA 30 Total Test Time Hours = 3000 TOTAL Failures for 0.45 pm FPGA 0 Table 25: Temperature Cycle Number of Cycles/Failures Date Number Test Product Package Wafer Lot Code of Units Cycles 200 500 1000 2000 Cycles

(-65°C - +1502C)

A40MX04 PLCC84 2XZR24206.5 26 1000 0 0 0 26000 A40MX04 PLCC84 2ACR23038.3 26 1000 0 0 0 26000 A42MX09 PQFP160 2ACT210121 30 1000 0 0 0 30000 A42MX16 PQFP160 2XZR25104.1 26 1000 0 0 0 26000 A42MX36 PQFP208 2ACT110221 27 1000 0 0 0 27000 TOTAL Units for 0.45 Mm FPGA = 135 Total Test Cycles = 135000 TOTAL Failures for 0.45 lIm FPGA 0 22 Reliability Report Revision 5

MOM eI 0.35 pm FPGA Reliability Summary Table 26: High Temperature Operating Life (HTOL)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX161, 2 CQFP208 2ACW210771 105 615 (2) 0 0 A54SX16 PQFP208 2ACT110031 74 2000 0 0 0 0 148000 A54SX16 PQFP208 2XZR402521 38 1000 0 0 0 38000 A54SX16 PQFP208 2ACU420072 99 1000 0 0 0 99000 A54SX16 PQFP208 2ACT100081 81 2000 0 0 0 0 162000 A54SX16P PQFP208 2ACT141821 45 1000 0 0 0 45000 1 27675 A54SX32 CQFP208 2ACU390881 45 615 0 0 A54SX32' CQFP208 2ACT500021 45 615 0 0 27675 A54SX32 PQFP208 2ACV103721 88 1000 0 0 0 88000 A54SX32 PQFP208 2XZT091468 43 2000 0 0 0 0 86000 A54SX32 PQFP208 2ACT330111, 88 1000 0 0 0 88000 2ACT330101, 2HCU462006 TOTAL Units for 0.35 Mm FPGA = 751 Total Test Time Hours = 809350 TOTAL Failures for 0.35 pm FPGA 0 Notes:

1. Tested at 1500C. Equivalent hours correspondingto 1250C were used to calculate the FIT rates.

2. ProductA54SX16, run 2ACW210771; the group C lot was started with 77 units and two devices failedduring functional test. The failure analysis with the two failure devices was started to narrow down the failure location and find the root cause of failure. Bench setup testing was done to reproduce the failure seen on the tester. Unfortunately, the two devices in FA, plus one more reference unit from the same lot, were misplaced in the lab and got lost during the Actel facility move from Sunnyvale to Mountain.View. The devices may have been scrapped by mistake as reject parts.

Therefore, the failure analysis could not be continued. An additional 29 units from the same inspection lot were submitted for full group C process and all passed.As a result, this group C qualification was passed with 105(2) result based on the L TPD(5) criteria.Actel TRB approved this group C result, and agreed this was a one-time accident due to the facility move, which should not recur with the currently establishedhandlingprocedure for FA devices.

Table 27: Low Temperature Operating Life (LTOL)

Test HourslFailures Date Number Test Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Unit Hours A54SX32 PQFP208 2ACT330111, 88 1000 0 0 0 88000 2ACT330101, 2HCU462006 TOTAL Units for 0.35 pm FPGA = 88 Total Test Time Hours = 88000 TOTAL Failures for 0.35 pm FPGA = 0 Reliability Report Revision 5 23

Table 28: Biased Humidity (HAST)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours A54SX32 BGA329 2ACU211641 9941 81 100 0 0 8100 9942 9943 A54SX16 PQFP208 2ACU241341 9947 84 100 0 0 8400 2ACU420072 0002 2ACU222448 0004 A54SX32 BGA329 2ACU410201 0013 76 100 0 0 7600 0014 0015 TOTAL Units for 0.35 pIm FPGA = 241 Total Test Time Hours = 24100 TOTAL Failures for 0.35 pm FPGA = 0 Table 29: Unbiased Humidity (HAST)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours A54SX16 PQFP208 2ACU241341 9947 84 100 0 0 8400 2ACU420072 0002 2ACU222448 0004 TOTAL Units for 0.35 pm FPGA = 84 Total Test Time Hours = 8400 TOTAL Failures for 0.35 pm FPGA = 0 Table 30: Temperature Cycle Number of CycleslFailures Date Number Test Product Package Wafer Lot Code of Units Cycles 200 500 1000 2000 Cycles

(-65°C - +150°C)

A54SX16 PQFP208 2ACU241341 9947 93 1000 0 0 0 93000 2ACU420072 0002 2ACU222448 0004 A54SX32 BGA329 2ACU410201 0013 76 1000 0 0 0 76000 2ACU410201 0014 2ACU410201 0015 A54SX32 PQFP208 2HCU462006 0010 76 1000 0 0 0 76000 2HCU410216 0017 2HCV022691 0017 TOTAL Units for 0.35 pm FPGA = 245 Total Test Cycles 245000 TOTAL Failures for 0.35 pm FPGA = 0 24 Reliability Report Revision 5

McteI0 0.25 pm MEC FPGA Reliability Summary Table 31: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX32A PQFP208 T25J002 80 1000 0 0 0 80000 A54SX32A PQFP208 T25JP03 88 1000 0 0 0 88000 A54SX32A PQFP208 T25J002, P05, 50 500 0 0 25000 P04 A54SX72A 1 .2 CQFP208 T25K065 77 615 (1) 0 47355 A54SX72A PQFP208 T25KO01 88 1000 0 0 0 88000 A54SX72A PQFP208 T25K065 77 615 0 0 47355 A54SX72A PQFP208 T25KP04 28 1000 0 0 0 28000 RT45SX32S CQFP208 T25JSP03 8 2000 0 0 0 0 16000 RT54SX32S CQFP208 T25JSOO1 8 4000 0 0 0 0 32000 RT54SX32S CQFP208 T25JS001 25 1000 0 0 0 25000 RT54SX32S CQFP208 T25JSP03 24 1000 0 0 0 24000 RT54SX32S 1 CQFP208 T25JSP03 52 615 0 0 31980 RT54SX32S CQFP208 T25JS004 22 2000 0 0 0 0 44000 RT54SX32S CQFP208 BP1037101 100 1000 0 0 0 100000 RT54SX32S CQFP208 T25JS004 20 1000 0 0 0 20000 RT54SX32S 1 CQFP256 T25JSP03 76 615 0 0 46740 RT54SX32S 3 COFP208 BP0083301, 150 1000 0 1 1(2) 149250 T25JS004, T25JSOO1(KM1)

RT54SX72S CQFP208 T25KS005 22 1000 0 0 0 22000 RT54SX72S1, 2 CQFP256 T25KS005 80 615 0 (1) 49200 TOTAL Units for 0.25 prm MEC FPGA = 1075 Total Test Time Hours = 963880 TOTAL Failures for 0.25 pm MEC FPGA = 2 Notes:

1. Tested at 1500C. Equivalent hours correspondingto 125&C were used to calculatethe FIT rates.

2. Product A54SX72A, run T25K065, and product RT54SX72S, run T25KS005; the failures determined were EOS.

3. K-antifuse failed at 250 hours0.00289 days 0.0694 hours 4.133598e-4 weeks 9.5125e-5 months ,F-antifuse failure at 1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months ,and 2 ESD failures at 1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months .

Reliability Report Revision 5 25

Table 32: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX32A PQFP208 T25J002, P05, P04 80 1000 0 0 0 80000 A54SX32A PQFP208 T25JP03 88 1000 0 0 0 88000 A54SX32A PQFP208 T25J002, P05, P04 50 500 0 0 25000 RT54SX32S* CQFP208 BP0083301, 149 250 0 1 37250 T25JS004, T25JS001(KM1)

A54SX72A PQFP208 T25K001 88 1000 0 0 0 88000 A54SX72A PQFP208 T25KPO4 28 1000 0 0 0 28000 TOTAL Units for 0.25 pm MEC FPGA = 483 Total Test Time Hours = 346250 TOTAL Failures for 0.25 pm MEC FPGA = 0 Note: *One K-antifuse failedat 250 hours0.00289 days 0.0694 hours 4.133598e-4 weeks 9.5125e-5 months Table 33: Biased Humidity (HAST)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours A54SX32A PQFP208 T25J002, P05, P04 80 100 0 0 8000 A54SX72A PQFP208 T25KP04 28 100 0 0 2800 TOTAL Units for 0.25 pm MEC FPGA = 108 Total Test Time Hours= 10800 TOTAL Failures for 0.25 pm MEC FPGA 0 Table 34: Temperature Cycle Number of Cycles/Failures Date Number Test I I I I Product Package Wafer Lot Code of Units Cycles 200 1 500 1 1000 2000 Cycles

(-65°C - +150°C)

A54SX32A PQFP208 T25J002, P05, P04 80 1000 0 0 0 80000 A54SX72A PQFP208 T25KP04 28 1000 0 0 0 28000 TOTAL Units for 0.25 pm MEC FPGA = 108 Total Test Cycles = 108000 TOTAL Failures for 0.25 pm MEC FPGA = 0 26 Reliability Report Revision 5

IRctelI 0.25 pm Flash FPGA Reliability Summary Table 35: High Temperature Operating Life (HTOL)

Test HourslFallures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A500K130 BGA272 ZA026941 0039, 76 1000 0 0 0 76000 ZA035953 0040 ZA034979 A500K130 BGA272 ZA051811 80 1000 0 0 0 80000 A500K270 BGA456 ZA027920 28 1000 0 0 0 28000 A500K130 BGA272 ZA051811 120 1000 0 0 0 120000 A500K130 BGA272 ZA051811 80 1000 0 0 0 80000 A500K130 BGA272 ZA049887 80 1000 0 0 0 80000 TOTAL Units for 0.25 pm Flash FPGA = 464 Total Test Time Hours 464000 TOTAL Failures for 0.25 pm Flash FPGA = 0 Table 36: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A500K130 BGA272 ZA026941 0039, 76 1000 0 0 0 76000 ZA035953 0040 ZA034979 TOTAL Units for 0.25 pm Flash FPGA = 76 Total Test Time Hours = 76000 TOTAL Failures for 0.25 pm Flash FPGA = 0 Table 37: Endurance Number of Cycles/Failures Product Package WaferLot Code of Units Cycles 50 100 500 1000 Cycles Room Temperature A50OK130 I0GA272 IZA026941 15 5 5 TOTAL Units for 0.25 pm Flash FPGA 15 ] Total Number of Cycles = 750 TOTAL Failures for 0.25 pm Flash FPGA = 0 Table 38: Retention 225°C Unbiased 100% Programmed Test Hours/Failures Date Number Test Unit Product Package WaferLot Code of Units Time 168 500 1000 2000 Hours A500K130 CGA272 ZA026941 9 1000 0 0 0 9000 TOTAL Units for 0.25 pm Flash FPGA = 9 Total Test Time Hours = 9000 TOTAL Failures for 0.25 pm Flash FPGA = 0 Reliability Report Revision 5 27

Table 39: Retention 225*C Unbiased 100% Erased

-Test Hours/Failures Date Number Unit Product Package Wafer Lot Code of Units Test Time 168 500 1000 2000 Hours A50OK130 CGA272 ZA026941 8 1000 0 0 0 8000 TOTAL Units for 0.25 pIm Flash FPGA = 8 Total Test Time Hours = 8000 TOTAL Failures for 0.25 pm Flash FPGA = 0 28 Reliability Report Revision 5

IActel 0.25 pm UMC FPGA Reliability Summary Table 40: CMOS Reliability-High Temperature Operating Life (HTOL)

Test Hoursl Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 3000 Hours RTSX32SU1 CQFP208 D122H1 0434 149 4,781 0 0 0 0 0 712402 1 0 0 0 0 1912 RTSX32SU CQFP208 D122H1 0434 1 1,912 RTSX32SU 1 CQFP208 D122H1 0434 150 4,781 0 0 0 0 0 717182 1 10,412 0 0 0 0 0 20824 RTSX32SU CQFP208 D122H1, 0434, 2 DlJW21 0442 RTSX32SU 1 CQFP208 D122H1, 0434, 148 31,237 0 0 0 0 0 4623009 D1JW21 0442 RTSX72SU1 CQFP208 DIAYH1, 0519, 1 15,618 0 0 0 0 0 15618 DIKT11 0445 RTSX72SU1 CQFP208 D1AYH1, 0519, 73 31,237 0 0 0 0 0 2280268 DlKT11 0445 RTSX72SU 1 CQFP208 DlAYHI, 0519, 5 20,824 0 0 0 0 0 104122 D1KT11 0445 RTSX32SU1 CQFP208 D11OAl - 68 0.91 62 RTSX72SU 1 CQFP208 DOYMJ1 - 32 0.91 29 RTSX32SU 1 CQFP208 D122H1 - 100 0.91 91 RTSX72SU1 CQFP256 DIJW01 - 35 54 1886 1 54 5389 RTSX32SU CQFP256 D1HLK1 - 100 RTSX32SU 1 CQFP208 D110A1 - 100 4.2 420 1 16168 RTSX32SU CQFP208 D110A1 - 100 162 RTSX32SU' CQFP208 D110A1 - 98 1.83 179 RTSX32SU1 CQFP208 D11OAl - 100 1.83 183 Notes:

1. As part of antifuse reliabilitytesting HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 pm) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the following assumptions Voltage Acceleration:

Tests where VCCA > VccA(max) (3.0 V) have been ignored

Tests where VCCA = 2.5 V to 3.0 V, voltage accelerationfactorfor these tests was assumed to be 1.

Temperature Acceleration:

Stress Temperature = Junction Temperature (i.e. Tstress = Tj).

The bum-in hours have been normalizedto a Tj of 1250C (i.e. 106 units @ Tj 1450C bum-in time 168 hrs is equivalent to 106 units @ Tj 1250C bum-in time 446.105 hrs)

2. ESD failures are representedin parentheses.

Reliability Report Revision 5 29

Table 40: CMOS Reliability-High Temperature Operating Life (HTOL) (Continued)

Test Hoursl Failures Date Number Test Unit Product Package WaferLot Code of Units Time 168 500 1000 2000 3000 Hours RTSX72SU1 CQFP208 DOYMJ1 - 68 0.91 62 1 0.9 91 RTSX72SU CQFP208 DOY311 - 100 RTSX32SU1 CQFP256 D122H1 0441 100 54 5389 RTSX32SUl CQFP208 D19S61 0450 100 54 5389 1 0.91 91 RTSX72SU CQFP208 D1AYH1 - 100 RTSX32SUl CQFP208 DIAYJ1 0450 100 54 5389 RTSX32SU 1 CQFP208 D1AYJ1 0502 100 54 5389 RTSX72SU' CQFP208 D1HLH4 0504 100 54 5389 RTSX72SU' CQFP208 D1HLJI 0446 100 54 5389 1 5389 RTSX32SU CQFP256 DIHL-I 0507 100 54 RTSX72SU 1 CQFP208 D1lJW1 0501 100 54 5389 RTSX32SU 1 CQFP208 DlJW21 0451 100 54 5389 1 5389 RTSX32SU COFP208 D1JW21 0452 100 54 RTSX32SU1 CQFP208 D1JW21 0511 100 54 5389 RTSX32SU' CQFP208 D1JW21 0512 100 54 5389 RTSX32SU' COFP208 D1JW21 0523 100 54 5389 RTSX32SU1 CQFP256 DlJW21 0518 100 54 5389 1 (1) 5389 RTSX72SU CQFP208 DlKT11 0515 100 54 RTSX72SU 1 CQFP208 D1MM81 0519 100 54 5389 1 5389 RTSX72SU CQFP256 D1MM91 0513 100' 54 RTSX72SUI CQFP256 D1N2W1 0520 100 54 5389 Notes:

1. As part of antifuse reliabilitytesting HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 gum) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation basedon the following assumptions Voltage Acceleration:

Tests where VCCA > VCCA(max) (3.0 V) have been ignored

Tests where VCCA = 2.5 V to 3.0 V, voltage accelerationfactor for these tests was assumed to be 1.

Temperature Acceleration:

Stress Temperature = Junction Temperature (i.e. Tstress = Tj).

The burn-in hours have been normalizedto a Tj of 1250C (i.e. 106 units @ Tj 1450C burn-in time 168 hrs is equivalent to 106 units @ Tj 1250C bum-in time 446.105 hrs)

2. ESD failures are representedin parentheses.

30 Reliability Report Revision 5

!ActelI Table 40: CMOS Reliability-High Temperature Operating Life (HTOL) (Continued)

Test Hoursl Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 3000 Hours RTSX72SU1 CQFP256 D1N8A1 0517 100 54 5389 RTSX32SU1 CQFP256 D1N8F1 0518 100 54 5389 RTSX72SU 1 CQFP256 DIP8T1 0522 100 54 5389' 1 54 5389 RTSX32SU CQFP256 D1P8W.1 0531 100 RTSX32SU 1 CQFP208 D1AYJ1 0450 80 321 0 25664 RTSX72SU' CQFP208 D1HLJ1 - 79 321 0 25343 1 (1) 133000 RTSX72SU CQFP208 DOY311 0410 133 1,000 RTSX72SU1 CQFP208 DOY311 0410 8 168 0 1344 RTSX32SU 1 CQFP208 D19S61 0436 80 615 (1) 49181 1 22680 RTSX32SU CQFP208 D110A1 - 135 168 0 RTSX32SU1 COFP256 D122H1 - 100 1000 0 0 0 100000 1 22000 RTSX32SU CQFP208 D1AYJ1 0504 22 1000 0 0 0 RTSX32SU 1 CQFP208 D1JW21, 0519, 150 750 0 0 112500 D1AYJ1 0502 RTSX72SU' CQFP256 DIN2W1 - 77 1000 0 0 0 77000 1 112500 RTSX32SU CQFP208 DIJW21, 0519. 150 750 0 0 D1AYJ1 0502 TOTAL Units for 0.25 pm FPGA = 4744 Total Test Time Hours = 9299758 TOTAL Failures for 0.25 pm FPGA = 0 CMOS failures observed Notes:

1. As part of antifuse reliabilitytesting HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 pm) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculationbased on the following assumptions Voltage Acceleration:

Tests where VCcA > VccA(max) (3.0 V) have been ignored

Tests where VCCA = 2.5 V to 3.0 V,voltage accelerationfactor for these tests was assumed to be 1.

TemperatureAcceleration:

Stress Temperature = Junction Temperature(i.e. Tstress = Tj).

The bum-in hours have been normalized to a Tj of 125 0C (i.e. 106 units @ Tj 1450C bum-in time 168 hrs is equivalent to 106 units @ Tj 1250C burn-in time 446.105 hrs)

2. ESD failures are representedin parentheses.

Reliability Report Revision 5 31

Table 41: CMOS Reliability Low Temperature Operating Life (LTOL)

Test HourslFailures Number Test Unit Product Package Wafer Lot Date Code of Units Time 168 500 1000 2000 3000 Hours RTSX32SUI CQFP208 D122Ht 0434 149 500 0 0 74500 1 75000 RTSX32SU CQFP208 D122H1 0434 150 500 0 0 1 0 450000 RTSX72SU CQFP208 DIAYH1, 0445, 0519 75 6000 0 0 0 0 D1KT11 1 0 760000 RTSX32SU CQFP208 D122H1, 0434,0442 152 5000 0 0 0 0 D1JW21 1

RTSX32SU CQFP208 D122H1, 0434, 0442 2 4000 0 0 0 0 0 8000 DlJW21 1 67000 RTSX72SU CQFP256 DOY311 0410 134 500 0 0 1

RTSX72SU CQFP256 DOY311 0410 8 168 0 1344 1

RTSX32SU CQFP256 D19S61 0436 6 1000 0 0 0 6000 1

RTSX72SU CQFP208 DOYMJ1 - 100 500 0 0 50000 1 16800 RTSX72SU CQFP208 DOY311 --- 100 168 0 RTSX72SUl CQFP208 D1AYH1 -- 100 168 0 16800 1

RTSX32SU CQFP208 D122H1 -- 100 168 0 16800 1

R-SX32SU CQFP208 D1JW21, 0519, 0502 150 1000 0 0 0 150000 D1AYJI 1

RTSX32SU CQFP208 D1JW21, 0519. 0502 150 500 0 0 75000 IDAYJ1 TOTAL Units for 0.25 pm FPGA = 1376 Total Test Time Hours = 1767244 TOTAL Failures for 0.25 pm FPGA = 0 CMOS failures Note: L TOL data from antifuse reliabilitytesting performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 pm).

Table 42: Temperature Cycle I I INumber I of Cycles/Failures.

Number Test I I I Product Package Wafer Lot of Units I Cycles 200 500 1000 1 2000 Cycles

(-651C - +150°C)

RTSX32SU CQFP208 D11OAl 68 100 6800 RTSX72SU CQFP208 DOYMJ1 68 100 6800 RTSX32SU CQFP208 D11OAll 135 100 13500 TOTAL Units for 0.22 pm FPGA = 271 Total Test Cycles = 27100 TOTAL Failures for 0.25 pm FPGA = 0 32 Reliability Report Revision 5

MActel Antifuse Reliability Overview Failure rates described in this section refer only to the antifuse portion for UMC 0.25 pm RTSX32-SU and RTSX72-SU Actel FPGA products programmed using the standard programming algorithm.

In the ideal case, all the testing would have been performed on these devices alone. However because of their high cost and lower availability, additional lifetests have been performed on the commercial device type A54SX72A (UMC 0.22 pm). Antifuse failures have been observed in both the military (RTSX32-SU and RTSX72-SU) devices as well as in the commercial (A54SX72A) devices.

Antifuse FIT rate calculator: A failure rate calculator in the form of an excel spreadsheet can be requested. The statistical procedure used in the calculator to analyze.the lifetest data is called the Maximum Likelihood Method (MLE). The model assumed for antifuse failures is a Weibull cumulative failure distribution as a function of time t (in hours) for n antifuses (EQ 1). The scale factor is given by a (hours) and the shape factor is given by f3(dimensionless).

F(Q) = 1- exp[(-n)(-+/- 01 EQ 1 The MLE shape factor was found to be less than one for the antifuses, describing a decreasing failure rate situation. A cumulative failure time model for the antifuse types where failures have been detected is therefore given by

" n1 and a 1 for the number and scale factor respectively for the failing antifuses in military FPGA

" n2 and a 2 for the number and scale factor respectively for the failing antifuse in commercial FPGA

" where as the same shape factor 0 has been assumed for both military and commercial categories.

The maximum likelihood method was programmed in S-Plus (http://www.insightful.com) to determine the coefficients a 1, a 2, and 03for both military and commercial FPGAs in one pass. A simultaneous estimate of all three parameters was made with all available data.

The calculator allows the user to describe a particular FPGA design, along with mission parameters, and computes an averaged failure rate for the mission.

Average antifuse FIT for UMC 0.25 pm RTSX-SU FPGA products at a 60% confidence bound is a FIT of 23.

" FIT calculator version used 23 (UMC Standard Algorithm FIT Rate Calculator Data v2_3.xls, updated 3/10/06)

Total of 1 failure observed for medium timing perceptibility

" Parts are programmed with standard programming algorithm

" Standard Aerospace Industry Design used: Actel has provided design characteristics of 42 different Aerospace Industry FPGA programming designs. To provide a guideline, an average or standard design has been obtained by simply taking the average of the antifuses of the various types and using in the FIT rate calculator.

" Screen hours 500

" 10 years of mission life Reliability Report Revision 5 33

i 0.22 pm UMC FPGA Reliability Summary Table 43: CMOS High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX08A PQFP208 DC183 0012 50 1000 0 0 0 50000 A54SX08A PQFP208 D1X181 90 1000 0 0 0 90000 A54SX08A PQFP208 D1X191 84 1000 0 0 0 84000 A54SXO8A PQFP20B D7K052 W 2 90 1000 0 0 0 90000 A54SX32A PQFP208 D7682 14.15 0028 100 1000 0 0 0 100000 A54SX32A and PQFP208 D7682.14 (HS), 150 3340 0 0 0 0 501000 A54SX08A D7766.12 (HS),

D7682.15 (FS),

D7766.19 (FS),

DC183(HS)

A54SX72A PQFP208 D03TC1 101 2000 0 0 0 0 202000 A54SX72A PQFP208 D4F117 38 168 0 6384 A54SX72A PQFP208 DCT03.1 22 168 0 3696 A54SX72A FC484 1 D55011 26 168 0 4368 A54SX72A PQFP208 D09A21 77 516 0 0 39732 A54SX72A PQFP208 D09A21 19 168 0 3192 A54SX72A PQFP208 D03TC1(74), DOKA91 100 168 0 16800 (26)

A54SX72A PQFP208 DOKA91 100 168 0 16800 A54SX72A PQFP208 DOKA91 100 168 0 16800 A54SX72A PQFP208 DCT03.1 90 168 0 15120 A54SX72A PQFP208 DCT03.1 69 120 8280 A54SX72A and PQFP208 D2E131, D2E151, 76 1000 0 0 0 76000 A54SXO8A D1X171 Notes:

1. Engineeringpackage.

2. As part of antifuse reliabilitytesting, HTOL tests were performed on A54SX72A (UMC 0.22 prm) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the following assumptions.

Voltage Acceleration:

Tests r where VCcA > VCCA(max) (3.0 V) have been ignored rTests where VCCA = 2.5 V to 3.0 V, voltage accelerationfactor for these tests was assumed to be 1.

TemperatureAcceleration:

Stress Temperature = Junction Temperature (i.e., Tshmss = Tj).

The bum-in hours have been normalized to a Tj of 1250C (i.e., 106 units at Tj 145 0C bum-in time 168 hrs is equivalent to 106 units at Tj 1250C bum-in time, 446.105 hrs)

3. ESD/EOS represented in parentheses-High IccA current detected, device fully functional, and meets all AC specifications.

34 Reliability Report Revision 5

MActer Table 43: CMOS High Temperature Operating Life (HTOL) (Continued)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX72A PQFP208 DC0143 38 516 0 0 19608 A54SX72A CQFP256 DOFIJ1. 96 615 0 59040 A54SX72A CQFP256 DOF1J1.1 23 615 0 14145 2 106 446 0 47287 A54SX72A PQFP208 DIRCPI A54SX72A 2 PQFP208 DIRCP1 108 1328 0 0 0 143391 A54SX72A 2 PQFP208 D1JTT1 108 2439 0 0 0 0 263361 2 0 813 A54SX72A PQFP208 D14S71 1 813 0 A54SX72A 2 PQFP208 D14S71 131 2439 0 0 0 0 319447 A54SX72A 2 PQFP208 D1RCP1 200 813 0 0 162568 A54SX72A 2 PQFP208 D1JTT1 1 446 0 446 A54SX72A2 PQFP208 DIJTT1 1 2159 0 0 0 0 2159 2 0 0 0 0 257573 A54SX72A PQFP208 D1JTT1 97 2655 A54SX72A 2 PQFP208 DOHONI 100 0.65 65 2 94 0.66 62 A54SX72A PQFP208 D03TC1 A54SX72A 2 PQFP208 D09YJ1 100 2.05 205 A54SX72A 2 PQFP208 D09YJ1 98 1.98 194 2 274 A54SX72A PQFP208 D09YJ1 139 1.97 A54SX72A 2 PQFP208 D092A16 107 6.11 654 2 4448 A54SX72A PQFP208 D146W1 104 42.8 A54SX72A 2 PQFP208 DOKA91 90 6.11 550 A54SX72A 2 PQFP208 D1JTT1 99 446 0 44165 Notes:

1. Engineering package.

2. As part of antifuse reliabilitytesting, HTOL tests were performed on A54SX72A (UMC 0.22 pJm) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the following assumptions.

Voltage Acceleration:

Tests where VCCA > VCCA(max) (3.0 V) have been ignored Tests where VCCA = 2.5 V to 3.0 V, voltage accelerationfactor for these tests was assumed to be 1.

TemperatureAcceleration:

" Stress Temperature= Junction Temperature (i.e., Tst8 es = Tj).

" The burn-in hours have been normalized to a Tj of 1250C (i.e., 106 units at Tj 145 0C bum-in time 168 hrs is equivalent to 106 units at Tj 1250C bum-in time, 446.105 hrs)

3. ESD/EOS represented in parentheses-High IcCA current detected, device fully functional, and meets all AC specifications.

Reliability Report Revision 5 35

Table 43: CMOS High Temperature Operating Life (HTOL) (Continued)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX72A 2 PQFP208 D1AYG3 91 446 0 40596 2 0 0 0 2092 A54SX72A PQFP208 D1JTT1 1 2092 0 A54SX72A 2 PQFP208 D1JTT1 100 2655 0 0 0 0 265539 2 0 0 0 812548 A54SX72A PQFP208 DIJTT1 102 7966 0 2 0 286782 A54SX72A PQFP208 D1JTT1 108 2655 0 0 0 A54SX72A 2 PQFP208 D03TC1 101 2105 0 0 0 0 212602 2

A54SX72A PQFP208 D1JTT1 1 1774 0 0 0 1774 2 539044 A54SX72A PQFP208 D1JTT1 203 2655 0 0 0 0 A54SX72A 2 PQFP208 D1AYG3 108 1328 0 0 0 143391 2

A54SX72A PQFP208 DIAYG3 108 1328 0 0 0 143391 A54SX72A 2 PQFP208 D1AYG3 1 430 0 430 2 142063 A54SX72A PQFP208 D1AYG3 107 1328 0 0 0 A54SX72A 2 PQFP208 D1RCP1 108 5311 0 0 0 0 573564 A54SX72A 2 PQFP208 DIRCP1 108 5311 0 0 0 0 573564 TOTAL Units for 0.22 pm FPGA = 4770 Total Test Time Hours = 6402007 TOTAL Failures for 0.22 pm FPGA = 0 CMOS Failures Notes:

1. Engineeringpackage.

2. As partof antifuse reliabilitytesting, HTOL tests were performed on A54SX72A (UMC 0.22 pm) at varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the following assumptions.

Voltage Acceleration:

Tests where VCCA > VCCA(max) (3.0 V) have been ignored

Tests where VCCA = 2.5 V to 3.0 V voltage accelerationfactor for these tests was assumed to be 1.

TemperatureAcceleration:

" Stress Temperature = Junction Temperature (i.e., Tstres = Tj).

" The bum-in hours have been normalized to a Tj of 1250C (i.e., 106 units at Tj 1450C bum-in time 168 hrs is equivalent to 106 units at Tj 1250C burn-in time, 446.105 hrs)

3. ESD/EOS represented in parentheses-High ICCA current detected, device fully functional, and meets all AC specifications.

36 Reliability Report Revision 5

M4ctel Table 44: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A54SX08A PQFP208 DC183 0012 50 1000 0 0 0 50000 A54SX32A PQFP208 D7682 14.15 0028 100 1000 0 0 0 100000 A54SX72A PQFP208 DC0143 38 168 0 6384 A54SX72A and PQFP208 D2E13,D2E151, 76 1000 0 0 0 76000 A54SX08A DIX171 A54SX72A PQFP208 D4F117 38 168 0 6384 A54SX72A PQFP208 DCT03.1 22 168 0 3696 A54SX72A1 PQFP208 D03TC1. 101 2000 0 0 0 0 202000 A54SX72A1 PQFP208 D1JTT1 108 1000 0 0 0 108000 A54SX72A PQFP208 DOKA91 85 168 0 14280 2

A54SX72A FC484 D55011 26 168 0 4368 A54SX32A and PQFP208 DC183(HS) 150 1000 0 0 0 150000 A54SX08A TOTAL Units for 0.22 pm FPGA = 794 Total Test Time Hours = 721112 TOTAL Failures for 0.22 pm FPGA 0 Notes:

1. LTOL data from antifuse reliabilitytesting on A54SX72A (UMC 0.22 pm)

2. Engineeringpackage Table 45: Biased Humidity (HAST)

Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 500 Hours A54SX08A PQFP208 DC183 0012 50 100 0 0 5000 A54SX32A PQFP208 D7682 14.15 0028 100 100 0 0 10000 A54SX32A PBGA329 D26E61 0610 45 528 0 0 0 0 23760 TOTAL Units for 0.22 pm FPGA = 195 Total Test Time Hours 38760 TOTAL Failures for 0.22 pm FPGA = 0 Reliability Report Revision 5 37

Table 46: Temperature Cycle Number of Cycles/Failures Date Number Test Product Package Wafer Lot Code of Units Cycles 200 500 1000 2000 Cycles 2 1000 0 0 0 50000 A54SX08A PQFP20B DC183 0012 50 2 0 0 0 100000 A54SX32A PQFP208 D7682 14.15 0028 100 1000 A54SX72A 2 PQFP208 DC0143 38 500 0 0 19000 A54SX72A +08A 2 PQFP208 D2E131,D2E151, 76 1000 0 0 0 76000 DIX171 A54SX72A2 PQFP208 D4F117 38 500 0 0 19000 A54SX72A2 FC484 1 055011 26 1000 0 0 0 26000 A54SX32A + 08A 2 PQFP208 D7682.14 (HS), 150 1000 0 0 0 150000 D7766.12(HS)

D7682.15 (FS),

D7766.19(FS)

DC183(HS)

A54SX32A 2 TQFP176 BP34640-1 & DIJAl 0515, 77 1000 0 0 0 77000 0516, 0517 A54SX32A 3 PBGA329 D26E61 0610 22 1000 0 0 0 22000 TOTAL Units for 0.22 pm FPGA = 577 Total Test Cycles = 539000 TOTAL Failures for 0.22 pm FPGA = 0

1. Engineeringpackage.

2. (-650 C - + 1500C)

3. (-550C - +1250C) 38 Reliability Report Revision 5

94ctel 0.22 pm Flash FPGA Reliability Summary Table 47: High Temperature Operating Life (HTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours APA1000 PBGA456 M279F, M279C 43 1000 0 0 0 43000 APA750 PBGA456 M1T74, M3AA6 86 1000 0 0 0 86000 APA750 PBGA456 MFJ2W, MFJ2S, 77 1000 0 0 0 77000 MFJ2T APA750 PBGA456 MFRGH, MFPQ8 18 1000 0 0 0 18000 APA750 PBGA456 MFR6H, MFPQ8 18 1000 0 0 0 18000 APA750 PBGA456 MFJ2W, MFJ2T, 77 1000 0 0 0 77000 MFJ2s APA750 PBGA456 M3AA4 0336 84 2000 (1) 0 (1) 0 167668 APA1000 CQFP352 MK3KA 0517 132 1115 0 0 0 147180 TOTAL Units for 0.22 pm Flash FPGA = 535 Total Test Time Hours = 631548 TOTAL Failures for 0.22 pm Flash FPGA = 0 Note: *Onedevice failed at 168 hours0.00194 days 0.0467 hours 2.777778e-4 weeks 6.3924e-5 months andit was confirmed due to ESD. The second one failed at 1500 hours0.0174 days 0.417 hours 0.00248 weeks 5.7075e-4 months and this failure resulted from testing a feature that has been removed from silicon. The test programs have subsequently been updated.

Table 48: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 10001 2000 Hours APA1000 PBGA456 M297F, M279C 26 1000 0 0 0 26000 APA750 PBGA456 MIT74, M3AA6 51 1000 0 0 0 51000 TOTAL Units for 0.22 pm Flash FPGA = 77 Total Test Time Hours = 77000 TOTAL Failures for 0.22 pIm Flash FPGA = 0 Table 49: Endurance Number of Cycles/Failures Date Number Test Product Package Wafer Lot Code of Units Cycles 50 100 500 1000 Cycles Room Temperature APA1000 I CGA391 M297F, M279C 30 500 0 0 0 15000 APA750 CGA391 ]MFJ2W, MFJ2S, MFJ2T 30 500 0 0 0 15000 TOTAL Units for 0.22 pm Flash FPGA = 60 Total Test Cycles = 30000 TOTAL Failures for 0.22 pm Flash FPGA = 0 Reliability Report Revision 5 39

Table 50: Retention 225°C Unbiased 100% Programmed Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 72 500 1000 3000 Hours APA1000 CGA391 MAE49, MC147, MC148 73 3000 0 0 0 0 219000 APA750 CGA391 MFJ2W, MFJ2S, MFJ2T 12 1000 0 0 0 12000 TOTAL Units for 0.22 pm Flash FPGA = 85 Total Test Time Hours = 231000 TOTAL Failures for 0.22 pm Flash FPGA 0 Table 51: Retention 225°C Unbiased '100% Erased Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 72 500 1000 3000 Hours APA1000 CGA391 MAE49, MC147, MC148 73 3000 0 0 0 0 219000 APA750 CGA391 MFJ2W, MFJ2S, MFJ2T 73 1000 0 0 0 73000 TOTAL Units for 0.22 pm Flash FPGA = 146 Total Test Time Hours = 292000 TOTAL Failures for 0.22 pm Flash FPGA 0 Table 52: Temperature Cycle Number of Cycles/Failures Date Number Test Product Package Wafer Lot Code of Units Cycles 200 500 1000 2000 Cycles

(-55°C - +1250C)

APA750O PBGA456 M3AA4 116 1 1000 0 0 0 16000 TOTAL Units for 0.22 pm Flash FPGA 16 Total Test Cycles 16000 TOTAL Failures for 0.22 pm Flash FPGA = 0 40 Reliability Report Revision 5

R4ctel 0.15 pm FPGA Reliability Summary Table 53: High Temperature Operating Life (HTOL)

Test HourslFailures Wafer Date Number Test Test Time Unit Product Package Lot Code of Units Time Tj°C @Tj 125 0C 168 500 1000 2000 Hours AX1000 PQFP208 D03121, 129 1000 125 1000 0 0 0 129000 D03131, D04CA1 AX1000 PQFP208 D0971-11, 77 1000 125 1000 0 0 0 77000 D097J1 AX2000 FPGA896 DOHGC1, 38 1000 125 1000 0 0 0 38000 DOH3M6 AX2000 FPGA896 D16T91 0431 22 1000 125 1000 0 0 0 22000 AX2000 FPGA896 D2A5A1 0620 77 1000 125 1000 0 0 0 77000 4

RTAX1000S CQFP352 D1GAH1 0444, 98 1000 132 1423 0 (4)1 0 133762 0507 4

RTAX2000S CQFP352 D1L9R1 0506 87 1000 132 1423 0 (2)1 0 120955 4

RTAX1000S CGA624 D1GAH1 0444 150 1000 132 1423 (1)2 (5)2 0 204912 4

RTAX1000S CGA624 DIGAH1 0444 28 1000 132 1423 0 13 0 38421 4

RTAX1000S CGA624 DIGAH1 0444 120 6000 132 8538 0 0 0 0 1024560 4

RTAX2000S CGA1152 DIPPY1 6 1000 132 1423 0 0 0 8538 4

RTAX2000S CQFP352 DIN9H1 6 1000 132 1423 0 0 0 8538 RTAX2000S 4 CQFP352 D1GAG1 14 168 132 239 0 3346 RTAX2000S 4 CQFP352 D1N9H1 14 168 132 239 0 3346 RTAX2000S 4 CQFP352 D21PH1 14 168 132 239 0 3346 Notes:

1. ESD representedin parentheses - ESD failuresdue to high ESD levels on test loadboard sockets. Failureanalysis was completed and to improve the ESD environment during the testing and programming flow, Acte/'s CQFP test socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15 V.

Actel has replacedall CQFPsocket lids in our test and programming facility with these "ESD-Friendly"lids. Actel issued PCN0512 for ESD-FriendlyLid Replacement for CQFPProgrammingModules.

2. Continuity failures caused by contention problems with the bum-in driver and the device. Failure analysis was completed and contention was fixed on the bum-in board adaptor.

3. CMOS failure happened at 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months . Failure analysis concluded the root cause as - Incomplete oxide etch during fabricationprocess.

4. HTOL data summarized above for CMOS FIT calculationbased on the following assumptions Voltage Acceleration:

VCCA = 1.6 V, voltage accelerationfactor for these tests has been assumed to be 1.

Temperature Acceleration:

Stress Temperature = Junction Temperature (i.e. Tstress = Tj).

The bum-in hours have been normalized to a Tj of 1250C (i.e. 100 units @ Tj 1320C burn-in time 1000 hrs is equivalent to 100 units @ Tj 125*C bum-in time 1423.015 hrs)

Reliability Report Revision 5 41

Table 53: High Temperature Operating Life (HTOL) (Continued)

Test Hours/Failures Wafer Date Number Test Test Time Unit 0

Product Package Lot Code of Units Time Tj°C @ Tj 125 C 168 500 1000 2000 Hours 4 0 52651 RTAX1000S CGA624 D1KH51 37 1000 132 1423 4 11384 RTAX1000S CQFP352 D1KH51 8 1000 132 1423 0 4 3346 RTAX2000S CQFP352 DIROGI 14 168 132 239 0 4 3346 RTAX2000S CQFP352 D1L9R1 14 168 132 239 0 4 0 3346 RTAX2000S CQFP352 DIPPY1 14 168 132 239 4 23900 RTAX250S CQFP352 D11H381 100 168 132 239 0 4

RTAXI000S CGA624 DIP01 150 1000 132 1423 0 0 0 213450 4

RTAX2000S CQFP352 D1N9H1 14 168 132 239 0 3346 4

RTAX1000S CGA624 D1KH51 24 168 132 239 0 5736 4

RTAX2000S CQFP352 D1NSG1 14 168 132 239 0 3346 4 6000 RTAX250S CQFP208 D1H381 6 1000 125 1000 0 0 0 4 0 0 78000 RTAX2000S CQFP352 D1KHN1 78 1000 125 1000 0 4 5736 RTAX1000S CQFP352 DlNR91 24 168 132 239 0 4

RTAX2000S CQFP352 D1KHN1 14 168 132 239 0 3346 4

RTAX2000S CQFP352 D21PH1 6 168 125 168 0 1008 TOTAL Units for 0.15pm FPGA = 1397 Total Test Time Hours = 2310665 TOTAL Failures for 0.15 pm FPGA = I Notes:

1. ESD representedin parentheses- ESD failures due to high ESD levels on test loadboard sockets. Failureanalysis was completed and to improve the ESD environment during the testing and programmingflow, Actel's CQFP test socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15 V.

Actel has replacedall CQFPsocket lids in our test and programming facility with these "ESD-Friendly"lids. Actel issued PCN0512 for ESD-FriendlyLid Replacement for CQFPProgrammingModules.

2. Continuity failures caused by contention problems with the bum-in driver and the device. Failure analysis was completed and contention was fixed on the bum-in board adaptor.

3. CMOS failure happened at 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months . Failure analysis concluded the root cause as - Incomplete oxide etch during fabricationprocess.

4. HTOL data summarized above for CMOS FIT calculationbased on the following assumptions Voltage Acceleration:

. VCCA = 1.6 V, voltage accelerationfactor for these tests has been assumed to be 1.

Temperature Acceleration:

Stress Temperature = Junction Temperature (i.e. Tstress = Tj).

The bum-in hours have been normalized to a Tj of 1250 C (i.e. 100 units @ Tj 132 0C burn-in time 1000 hrs is equivalent to 100 units @ Tj 1250C bum-in time 1423.015 hrs) 42 Reliability Report Revision 5

F4cteI Table 54: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours AX1000 PQFP208 D03121, 129 1000 0 0 0 129000 D03131, D040A1 AX1000 PQFP208 D097H1, D097J1 77 1000 0 0 0 77000 AX2000 FPGA896 DOHGC1, 38 1000 0 0 0 38000 D0H3M6 RTAX1000S CQFP352 DIGAH1 0444, 78 1000 0 (1)1 0 77000 0507 RTAX1000S CGA624 D1GAHI 144 250 0 36000 RTAX1000S CGA624 D1GAHI 150 250 (2)2 37000 RTAX1000S CGA624 DlPQ01 148 250 0 37000 RTAX1000S CGA624 DlPQ01 150 250 0 37500 RTAX2000S CQFP352 DIKHN1 78 168 0 13104 TOTAL Units for 0.15 pm FPGA = 992 Total Test Time Hours = 481604 TOTAL Failures for 0.15 pm FPGA = 0 Notes:

1. ESD representedin parentheses - ESD failures due to high ESD levels on test loadboard sockets. Failureanalysis was completed and to improve the ESD environment during the testing and programming flow, Actel's CQFPtest socket vendor manufacturedsocket lids with an ESD friendly polymer materialthat reduces the ESD charge to about 15V. Actel has replaced all CQFP socket lids in our test and programming facility with these "ESD-Friendly"lids. Actel issued PCN0512 for ESD-Friendly Lid Replacement for CQFPProgramming Modules.

2. Continuityfailures causedby contention problems with the burn-in driverand the device. Failure analysis was completed and contention was fixed on the bum-in boardadaptor.

Table 55: Biased Humidity (HAST)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours AX1000 PQFP208 D03121. 129 100 0 0 12900 D03131, DO4CA1 AX2000 FBGA896 DOHGC1, 38 100 0 0 3800 DOH3M6 TOTAL Units for 0.15 pm FPGA = 167 Total Test Time Hours = 16700 TOTAL Failures for 0.15 pm FPGA = 0 Reliability Report Revision 5 43

Table 56: Temperature Cycle

_Number of Test CycleslFallures Product Package Wafer Lot Date Code Number of Units Test Cycles I

200 1 500 II1000 2000 I

Cycles 0

(-65 C - +150*C)

AX1000 PQFP208 D03121, 129 500 0 0 64500 D03131, DO4CAl AX1000 PQFP208 D097H1, 77 500 0 0 38500 D097J1 AX2000 FBGA896 DOHGC1, 22 500 0 0 11000 DOH3M6 TOTAL Units for 0.15 gim FPGA = 228 Total Test Cycles = 114000 TOTAL Failures for 0.15 pm FPGA = 0 0.13 pm Flash FPGA Reliability Summary Table 57: High Temperature Operating Life (HTOL)

Test Hours/Failures Test Time Number Test @ Tj Unit Product Package Wafer Lot Date Code of Units Time Tj 0 C 125 0 C 168 500 1000 2000 Hours A3P060 FPGA256 ZA612052 0626 129 1000 133C 1495 0 0 0 192855 A3P250 FPGA256 ZA519154 0527 15 168 133C 251 0 3765 1

A3P250 FPGA256 ZA519154, 0532, 129 3000 133C 4485 0 0 0 0 578565 ZA519154.01, 0533, ZA523569, 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P250 FPGA256 ZA628252.05 0628 77 1000 133C 1495 0 0 0 115115 A3P400 FPGA256 ZA614042 0637 77 1000 133C 1495 0 0 0 115115 1 0 0 405189 A3P1000 FPGAG484 ZA546185, 0604, 129 2000 134 3141 0 0 ZA538175.02, 0602 ZA548138 0608, 0609 A3P1000 FPGAG484 ZA63718002 0640 77 1000 134 1570 0 0 0 120890 TOTAL Units for 0.13 pm FPGA = 633 Total Test Time Hours 1531494 TOTAL Failures for 0.13 pm FPGA = 0 Note: Initial 1000 hrs HTOL completed per qualificationrequirement, HTOL was continued up to 3000 hours0.0347 days 0.833 hours 0.00496 weeks 0.00114 months for A3P250, all units passed

2000 hours0.0231 days 0.556 hours 0.00331 weeks 7.61e-4 months for A3P1000, all units passed 44 Reliability Report Revision 5

MActel Table 58: Low Temperature Operating Life (LTOL)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 168 500 1000 2000 Hours A3P250 FBGA256 ZA519154 0527 15 168 0 2520 1 2000 0 0 0 0 258000 A3P250 FBGA256 ZA519154, 0532, 129 ZA519154.01, 0533, ZA523569, and 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 FBGAG484 2 ZA546185, 0604, 129 1000 0 0 0 129000 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm FPGA = 273 Total Test Time Hours = 389520 TOTAL Failures for 0.13 prm FPGA = 0 Notes:

1. Initial 1000 hrs LTOL completed per qualification requirement;LTOL was continued up to 2000 hours0.0231 days 0.556 hours 0.00331 weeks 7.61e-4 months , all units passed.

2. G indicates lead-free.

Table 59: Temperature Cycle Product Package Wafer Lot D]te Code Number of Units Cycles Number of Test Cycles/Failures ITes 200 500 1000 2000 Cycles

(-55°C - +1251C)

A3P250 FBGA256 ZA519154, 0532, 129 1000 0 0 0 129000 ZA519154.01, 0533, ZA523569, and 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 FPGAG484* ZA546185, 0604, 77 1000 0 0 0 77000 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm FPGA = 206 Total Test Cycles = 206000 TOTAL Failures for 0.13 pm FPGA = 0 Note: *Gindicateslead-free.

Reliability Report Revision 5 45

Table 60: Biased Humidity (HAST)

Test Hours/Failures Date Number Test Unit Product Package Wafer Lot Code of Units Time 50 100 200 250 Hours A3P250 FBGA256 ZA519154 0527 22 264 0 0 0 0 5808 A3P250 FBGA256 ZA519154, 0532, 129 264 0 0 0 0 34056 ZA519154.01, 0533, ZA523569, and 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 FBGAG484* ZA546185, 0604, 77 264 0 0 0 0 34056 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm FPGA 228 Total Test Time Hours = 73920 TOTAL Failures for 0.13 pm FPGA = 0 Note: *G indicateslead-free.

Table 61: Endurance Number of CycleslFailures Product _

Package_ Wafer Lot

_ Date Code Number of Units Test Cycles 50 100 500 1000 Cycles Room Temperature A3P250 FBGA256 ZA519154 0527 5 3000 0 0 0 0 150000 A3P250 FBGA256 ZA519154, 0532, 129 550 0 0 0 70950 ZA519154.01 0533, ZA523569, 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 FBGAG484- ZA546185, 0604, 77 550 0 0 0 42350 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm Flash FPGA = 211 Total Test Cycles = 263300 TOTAL Failures for 0.13 Im Flash FPGA= 0 Note: *G indicateslead-free.

46 Reliability Report Revision 5

M4ctelI Table 62: Retention 250°C Unbiased 100% Programmed Test HourslFailures Number Test Unit Product Package Wafer Lot Date Code of Units Time 72 500 1000 3000 Hours A3P250 CQFP208 ZA519154 0527 45 168 0 7560 A3P250 CQFP208 ZA519154, 0532, 129 1000 0 0 0 129000 ZA519154.0, 0533, ZA523569,and 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 CQFP208 ZA546185, 0604, 77 500 0 0 8500 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm Flash FPGA = 251 Total Test Time Hours = 175060 TOTAL Failures for 0.13 pm Flash FPGA 0 Table 63: Retention 250°C Unbiased 100% Erased Test HourslFailures Date Number Test Unit Product Package Wafer Lot Code of Units Time 72 500 1000 3000 Hours A3P250 COFP208 ZA519154 0527 45 168 0 7560 A3P250 CQFP208 ZA519154, 0532, 129 1000 0 0 0 129000 ZA519154.01, 0533, ZA523569, and 0534, ZA523569.01 0536, 0537, 0538, 0541, 0543 A3P1000 CQFP208 ZA546185, 0604, 77 500 0 0 38500 ZA538175.02, 0602, ZA548138 0608, 0609 TOTAL Units for 0.13 pm Flash FPGA = 251 Total Test Time Hours = 175060 TOTAL Failures for 0.13 pm Flash FPGA = 0 Reliability Report Revision 5 47

List of Changes The following table lists critical changes that were made in the current version of the document.

Previous Version IChanges in current version (Revision 5, April 2007, 51000001-5/4.07) Page Q2 CY2006 ORT Report updates are not done quarterly, usually updated twice a year or by request from Actel (August 2006) Technical Review Board (TRB). Labels referencing quarter/year are being replaced with a revision number. This version of the ORT report is Rev 4.

51000001-4/8.06 Updated Table 1: FIT rates for following Device Technology have been updated 4

0.25 pm UMC CMOS FPGA 0.22 pm UMC Flash CMOS FPGA a0.15 pm UMC CMOS FPGA

0.13 pm Inineon Flash CMOS FPGA Updated Table 2: FIT rates for following Device Technology have been updated 5 0.25 pm UMC CMOS FPGA (RTSX-SU)

0.22 pm UMC Flash CMOS FPGA (ProASICl-&S)

0. 15 pm UMC CMOS FPGA (Axcelerator)

0. 15 pm UMC CMOS FPGA (RTAX-S)

0. 13 pm Infineon Flash CMOS FPGA (ProASIC3)

Updated Table 40: 0.25 pm UMC RTSX-SU HTOL data 29

Updated test time (added250 hrs) for RTSX32SU, CQFP208,WIL DIJW21 and DIAYJ1, DC 0519 and 0502:150 units, Test Time = 750, Unit Hrs = 112500 Added new data: RTSX32SU, CQFP208,WIL DIJW21 and D1AYJ1, DC 0519 and 0502, 150 units, Test Time = 750, Unit Hrs = 112500

Updated the TOTAL Units for 0.25 pm FPGA to 4744 and Total Test Time Hours=

9299758 Updated Table 41: 0.25 pm UMC RTSX-SU LTOL data 32

Updatedtest time (added500 hrs) for RTSX32SU, CQFP208,W/L DIJW21 and DIAYJ1, DC 0519 and 0502: 150 units, Test Time = 1000, Unit Hrs = 150000 Added new data:RTSX32SU, CQFP208, WIL DlJW21 and DIAYJI, DC 0519 and 0502, 150 units, Test Time = 500, Unit Hrs = 75000

Updated the TOTAL Units for 0.25 pm FPGA to 1376 and TOTAL Test Time Hours to 1767244 Updated Table 45: 0.22 pm UMC SX-A Biased Humidity (HAST) data 37

Added new data:A54SX32A, PBGA329, WIL D26E61, DC 0610, 45 units, Test Time =

528, Unit Hrs = 23760

Updatedthe TOTAL Units for 0.22 pm FPGA to 195 and TOTAL Test Time Hours to 38760 Updated Table 46: 0.22 pm UMC SX-A Temperature Cycle data 38

Added new data:A54SX32A, PBGA329, WIL D26E61, DC 0610, 22units, Test Cycles =

1000, Unit Cycles = 22000

Updatedthe TOTAL Units for 0.22 pm FPGA to 577 and Total Test Cycles to 539000

Removed the generic (-650 C - +1500 C) row and added footnotes for (-650C - +1500 C) and

(-550C - +1250 C) for each line in the table Updated Table 47: 0.22 pm UMC Flash APA HTOL data 39 Updated test time (added 500hrs) for APAIO00, CQFP352, WIL MK3KA, DC 0517, 132 units, Test Time = 1115 Unit Hrs = 147180

Updated the Total Test Time Hours = 631548 Previous Version IChanges in current version (Revision 5, April 2007, 51000001-514.07) Page 48 Reliability Report Revision 5

FActelI Q2 CY2006 Updated Table 50 and Table 51: 0.22 pm UMC Flash APA Retention Programmed and Erased 40 (August 2006)

The WIL numbers forAPAlO00, CGA391, 73 units was incorrectlystated as ZA026941, 51000001-4/8.06 correctedto MAE49, MC147, MC148.

Updated Table 53: 0.15 pm UMC Axcelerator and RTAX-S HTOL data 41

Updatedtest time (added 1000 hrs@1320 C) for RTAXIO00S, CGA624, WIL DIGAH1, DC 0444, 120 units, Test Time @ 1320C = 6000, Unit Hrs @ 125*C = 1024560

Updated test time (added832 hrs @132 0 C) for RTAX1000S, CGA624, W/L DIKH51, 37 units, Test Time @ 1320C = 1000, Unit Hrs @1250C = 52651

Updated test time (added 832 hrs @ 132 0C) for RTAXIO00S, CQFP352, WIL DIKH51, 8units, Test Time @ 1320 C = 1000, Unit Hrs @125*C = 11384

Added new data: AX2000, FPGA896, WIL D2A5A 1, DC 0620, 77 units, Test Time = 1000 @

125°C, Unit Hrs @ 125°C = 77000 Added new data:RTAXIO00S, CGA624, WIL D1KH51, 24 units, Test Time @ 132 0 C =

168, Unit Hrs @125C = 5736 Added new data: RTAX2000S, CQFP352, WIL DINSG1, 14 units, Test Time @ 132 0C =

168, Unit Hrs @ 125-C = 3346 Added new data: RTAX250S, CQFP208, WIL DIH381, 6 units, Test Time @ 1250 C =

1000, Unit Hrs @ 1250 C = 6000

Added new data: RTAX2000S, CQFP352,WIL DIKHNI, 78 units, Test Time @ 125 0C =

1000, Unit Hrs @ 125-C = 78000

" Added new data: RTAXIO00S, CQFP352,W/L DINR9I, 24 units, Test Time @ 132 0 C =

168, Unit Hrs @ 125*C = 5736

" Added new data: RTAX2000S, CQFP352, WIL DIKHN1, 14 units, Test Time @ 132*C =

168, Unit Hrs @ 1250C = 3346

" Added new data: RTAX2000S, CQFP352, WIL D21PH1, 6 units, Test Time @ 1250 C =

168, Units Hrs @ 125°C,= 1008

Updated the TOTAL Units for 0. 15 pm FPGA to 1397 and Total Test Cycles = 2310665 Updated Table 54: 0.15 pm UMC Axcelerator and RTAX-S LTOL data 43

Added new data:RTAX2000S, CQFP352, WIL DIKHNI, 78 units, Test Time = 168, Unit Hrs = 13104

Updated the TOTAL Units for 0.15 pm FPGA = 992 and Total Test Time Hours = 481604 Updated the TOTAL Units for 0. 131pm FPGA = 633 and Total Test Time Hours = 1531494 Updated Table 57: 0.13 pm IFX A3P HTOL data 44

Changed the table format to report Tj and Test Time during HTOL testing and Test Time at Tj 1250C

Added new data:A3P060, FPGA256, WIL ZA612052, DC 0626, 129 units, Test Time @

133-C = 1000, Unit Hrs @ 1250C = 192855 Added new data: A3P250, FPGA256, WIL ZA628252.05, DC 0628, 77 units, Test Time @

133-C = 1000, Unit Hrs @ 125CC = 115115

Added new data:A3P400, FPGA256, ZA614042, DC 0637, 77units, Test Time @ 1330 C =

1000, Unit Hrs @ 1250C = 115115 Updated Table 62 and Table 63: Removed text "Room Temperature" as these are run at 250"C 1 47 Reliability Report Revision 5 49

Previous Version Changes in current version (Q2 CY2006, August 2006, 51000001-4/8.06) Page 01 CY2006 Added tables Table 57 through Table 63 for 0.13 pm IFX CMOS FPGA (ProASIC3). 44-47 May 2006 Updated Table Table 53 and Table 54. 41.43 51000001-3

Added AX2000-FPGA896, WIL D16T91, DC0431 to Table 53.

Added RTAX-S Data to Table 53 and Table 54.

Updated Table 47. 39

Added APA1000-CO256, WIL MK3KI, DC 0517, 132 units, Test Time= 615, Unit Hrs=

81180.

Updated Table 40, 0.25 pm UMC RTSX-SU HTOL data. 29 Updated RTSX72SU, CQFP208, W/L DIAYH1 and DIKT11, DC 0519 and 0445:

73 units, Test Time = 31,237, Unit Hrs = 2280268

5 units, Test Time = 20,824, Unit Hrs = 104122 Added RTSX32SU, CQFP208, W/L DlJW21 and D1AYJ1, DC 0519 and 0502: 150units, Test Time = 500, Unit Hrs = 75000.

Added RTSX72SU, CQFP256, W/L D1N2WI, 77units, Test Time = 1000, Unit Hrs = 7000.

Updated Table 41, 0.25 pm UMC RTSX-SU LTOL data. 32 Added RTSX32SU, CQFP208, W/L DIJW21and D1AYJ1, DC 0519 and 0502:150 units, Test Time = 500, Units Hrs = 75000.

Updated RTSX32SU, CQFP208, W/L D122H1 and DIJW21, DC 0434 and 0442:

152 units, Test Time = 5000, Unit Hrs = 760000

2 units, Test Time = 4000, Unit Hrs = 8000 Updated RTSX32SU, CQFP208, W/L DIAYHI and D1KT11, DC 0445 and 0519: -*

. 75 units, Test Time = 6000, Unit Hrs = 450000.

Updated Table 3 ESD Performance for RTAX-S and ProASIC3. 6 Updated Table 2. 5

Updated 0.25 pm UMC CMOS FPGA (RTSX-SU) data

Updated 0. 15 pm UMC CMOS FPGA (Axcelerator) data Added 0.15 pm UMC CMOS FPGA (RTAX) data Added 0.13 pm IFX CMOS FPGA (ProASIC3)data Updated Table 1. 4

Updated 0.25pm UMC CMOS FPGA data Updated0.15 pm UMC CMOS FPGA data

Added 0. 13 pm IFX CMOS FPGA data Previous Version Changes In current version (01 CY2006, May 2006, 51000001-3/5.06) Page 02 CY2005 Note relating to UMC 0.25 pm RTSX-SU antifuse FIT rates added to Table 1. 4 August 2005 XL and DX devices in 0.8 pm CMOS FPGA were removed from Table 2 and Table 13. 5, 14 51000001-2 Removed "Table 9. Thermal Shock." Table had header only; no data. N/A Revised entire section "0.25 pm UMC FPGA Reliability Summary" and added new data from 29 UMC 0.25 pm RTSX-SU antifuse reliability testing.

Revised entire section "0.22 pm UMC FPGA Reliability Summary" and added new data from 34 UMC 0.22 pm A54SX72A antifuse reliability testing.

Started including the Date Codes for the packages used in the reliability studies. N/A so Reliability Report Revision 5

M4ctel Previous Version Changes in current version (Q2 CY2005, August 2005, 51000001-2/8.05) Page Q2 CY2005 The "ESD Performance" section data has been added. 6 August 2005 New ORT data has been added, 0.22 pm Flash FPGA (Table 45). 37 51000001-1 0.22/0.25 pm CMOS FPGA results have been updated with new test results. 25-39 Previous Version Changes in current version (02 CY2005, August 2005, 51000001-118.05) Page 03 CY2004 Product 1010A was removed from 1.0 pm FPGA, ACTI Family. 8 December 2004 All the earlier devices manufactured by TI were removed from 1.0 pm FPGA, ACTI, and ACT2 8 51000001-0 Families.

Industry standard nomenclature was used for the package names N/A All the FIT rates were checked and corrected as necessary N/A The "Group E Inspection-Generic Data (radiation hardness)" section has been added. 7 ESD performance data has been removed. N/A For more information, visit our website at www.actel.com.

Reliability Report Revision 5 51

ML071770456

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