Text

Quality & Reliability Guide
	ML071770454
Person / Time
Site:	Wolf Creek
Issue date:	03/31/2001
From:	; Actel Corp
To:	; Office of Nuclear Reactor Regulation
References
	ET 07-0022
	Download: ML071770454 (98)
	v • d • e

Enclosure 4 to ET 07-0022 Actel's Quality and Reliability Guide

_**ctel Quality & Reliability Guide March 2001

MCMe

~cteI Contents

1.

Overview of Actel's Quality and Reliability Guide......................I Actel's Commitment...............

2.

Actel's Quality Certifications........

PURE Certification...............

STACK International Registration....

QML Certification................

Plastic QML Certification..........

ISO 9002 Certification.............

Reliability Assurance System........

......................I

.2

.3

.4 3.

Q uality System..................................................

5 Contract Review.................................................

5 Document and Data Control.......................................

5 Control of Supplier and Subcontractor Quality.........................

5 Product Identification and Traceability...............................

5 Process Control.................................................

5 Control of Inspection, Testing, Measuring and Test Equipment............

6 Control of Nonconforming Products.................................

6 Corrective and Preventive Action System.............................

6 Control of Handling, Storage, Packaging, Preservation, and Delivery...... 6 Internal Quality Audit............................................

6 Training.......................................................

7 Servicing.......................................................

7 Statistical Process Control.........................................

7 Continuous Improvement Program..................................

7 Quality & Reliability Guide iii

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4.

Qualification Program...........................................

8 P urpose.......................................................

8 New Fab Process Technology.....................................

10 N ew Package..................................................

11 Large Die Qualification...................

12 Existing Package...............................................

12

5.

Quality & Reliability Testing.....................................

19 High Temperature Operating Life (HTOL)..........................

19 Highly Accelerated Stress Test (HAST).............................

28 Temperature Cycling/Thermal Shock...............................

33 Electrostatic Discharge (ESD)....................................

41 Latch-Up.....................................................

43 Radiation H ardness.............................................

43

6.

SPC Data Wafer Fabrication.....................................

44

7.

SPC Data Assembly............................................

44

8.

Reliability: FIT Rate............................................

45 Failure Rates and Mean Time to Failure............................

45

9.

Process Flow Comparisons for HiRel Devices 46

10. Customer PCN Flow............................................

52

11. RM A Process..................................................

53

12. FA Process...................................................

55 Appendices A.

Actel and the Antifuse-A Technical Backgrounder....................

57 Introduction...................................................

57 Antifuse vs. Memory-Based Programmable Logic.....................

59 Antifuse Technology............................................

60 Evolution Antifuse Alternatives....................................

62 User Benefits of Actel's Technology................................

64 Future Directions in Antifutse Technology...........................

65 Appendix A-The Structure of Antifuses.............................

66 Appendix B-The Hidden Cost of Reprogrammability..................

68 iv Quality & Reliability Guide

Contents wctel B.

C.

Oxide-Nitride-Oxide Antifuse Reliability.............................

71 Reliability of Actel Metal-to-Metal Antifuses..........................

78 Introduction...................................................

78 Antifuse Structure and Characteristics..............................

78 Reliability Characterization and Modeling...........................

82 Designing for Reliability.........................................

87 Process Monitoring for Reliability.................................

88 Product Screening for Reliability..................................

88 Product Testing for Reliability.....................................

89 C onclusion....................................................

90 R eferences....................................................

90 Quality & Reliability Guide v

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1.

Overview of Actel's Quality and Reliability Guide As a leader in programmable logic solutions, Actel has established and implemented aggressive quality and reliability objectives to ensure that all of its products exceed customer requirements.

In addition, it is Actel's goal to continuously improve the quality and reliability of its operations at all levels, from market research and product design to product delivery and customer service.

This commitment is reflected in Actel's company-wide policies, which are geared towards continuously improving all levels of operation and include:

0 Open, continuous communication between top executives, managers, and employees 0 Emphasis on cooperation and teamwork 0 Employee awareness, training, participation, and recognition 0 Measurement and auditing of processes M Follow-up, maintenance, and service 0 Internal-customer concept (all company employees act as both customers and suppliers to one another) 0 Job ownership and empowerment Actel's Commitment Actel is dedicated to providing superior programmable logic solutions and enabling designers to successfully advance to higher complexity designs with confidence.

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2. Actel's Quality Certifications Actel conforms to nationally and internationally recognized standards and demonstrates its competitive advantage with an enviable portfolio of quality and reliability certifications. Actel has achieved the following certifications and registrations:

0 PURE Certified - March 2000 N STACK International Registered-December 1999 0

QML Certified-May 1999 N Plastic QML Certified - September 1998 E

ISO 9002 Certified - May 1998 PURE Certification PURE, an acronym for PEDs (plastic encapsulated devices) Used in Rugged Environments, is an association of European equipment makers dedicated to quality and reliability. Members include Thomson-CSF, Ericsson, SAAB Dynamics, Ericsson SAAB Avionics, Bofors Missiles, and Celcius Technology. Members are committed to sharing data and results related to plastic components used in rugged environments. The association is also supported by the French and Swedish Ministries of Defense.

Actel's qualification is for the plastic quad flat pack (PQFP) package. This certification underscores Actel's commitment to quality, reliability, and continuous improvement in products, processes, and systems.

STACK International Registration STACK International is a group of multinational independent electronic equipment manufacturers who share experience, have similar workloads, and cooperate in precompetitive areas with each other and their suppliers to reduce both the cost to individual members and the risk of component ownership.

Members include Allied Signal, The Boeing Company (US), British Aerospace, Honeywell, Hughes Space and Communications, Italtel, Litton Guidance and Control System, Lockheed Martin, Lucent Technologies, Marconi Communications, Nortel Networks, Rockwell Collins, and Siemens Communications.

By being registered with STACK, Actel formally accepts the requirements of the STACK purchase specification - General Requirements for Integrated Circuits. Actel's standard qualification procedure, product monitoring program, and manufacturing process meet or exceed the specified requirements. We agree to supply products in accordance with the requirements when requested by a STACK Member STACK Registered suppliers include Actel, Altera, AMD, Atmel, Cypress, Fujitsu, Hitachi, Intel, Lattice, LSI Logic, Motorola, NEC, Siemens, TI, and Xilinx.

2 Quality & Reliability Report

Sctel QMIL Certification Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is an example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military, and space applications.

Many suppliers of microelectronic components have implemented QML as their primary worldwide business system. Use of this system not only assists in the implementation of advanced technologies, but also allows for reliable and cost-effective logistics support throughout the life cycles of QML products.

Plastic QML Certification Actel is committed to supplying the highest quality products for all types of high-reliability, military, and space applications by broadening the products offered with its Plastic QML Certification. Actel's QML plastic devices can be integrated into design applications that normally require high-cost ceramic packages, thereby providing designers with a low-cost solution. This certification also permits the integration of commercial and military production without compromising quality or reliability.

ISO 9002 Certification ISO standards, developed by the International Organization for Standardization, provide an international benchmark for quality systems. ISO registration demonstrates the establishment of a foundation for continuous improvement in manufacturing, test systems, and increased productivity. ISO 9002 registration requires compliance in: management responsibility, customer service, training, process control, inspection and testing, and internal quality audits.

ISO certification is a globally recognized benchmark that certifies the integrity of Actel's test and manufacturing process. Its ISO certification enables Actel to establish itself as a leader of high-quality FPGAs.

Quality & Reliability Report 3

OrcteI Reliability Assurance System1 To ensure that customers are satisfied with the supplied products, reliability assurance programs for semiconductor devices are used in the design, development, and manufacturing phases. The assurance program guarantees the following:

1. Actel ensures that target reliability is built into the products by conducting reviews and in-house qualification tests in the design and development stages.

2. Actel conducts in-process and final quality inspections during the design and manufacturing phases. We use the inspection results to further refine the design and production process.

I. For more information about Actel product reliabiliti; refer to the following documents beginning on page 57.

Actel and the Antifitse-A Technical Backgrounder Oxide-Nitride-Oxide Antihitse Reliability ReliabilitY ofActel Metal-to-Metal Anti/itses 4 Quality & Reliability Report

_7ctel

3. Quality System Actel maintains a quality system to ensure that products meet or exceed specified requirements.

Necessary equipment, controls, and processes are in place to ensure that we achieve the desired quality.

Contract Review A procedure for review of customer requirements is in place to ensure that Actel has the capability to meet contract and order requirements. Since we do not accept verbal orders, Actel's review procedure requires verification that customer requirements are adequately defined and documented.

Document and Data Control Actel has established procedures to maintain control of all documents and data that are originated both internally and externally. All specifications and changes of the information and data contained in these documents require sign-off by all affected functional areas. All product flows are under specification control and are available to prevent the use of invalid and/or obsolete documents.

Control of Supplier and Subcontractor Quality All suppliers and subcontractors are selected, approved, and controlled. Documented procedures are available to ensure that purchased and subcontracted products conform to specified requirements. Suppliers and subcontractors are selected on the basis of their ability to meet Actel's requirements, including having a robust quality system and meeting specific quality assurance requirements.

Product Identification and Traceability Procedures for identifying and tracing products from receipt and through all stages of production, storage, delivery, and installation are in place. An electronic system is utilized for efficient tracking of works-in-process and the inventory and shipping offinished goods.

Process Control All major process changes must be pre-approved by Actel before implementation. Actel has documented procedures that define manufacturing operations and ensure that equipment is used appropriately. All high reliability and in-house programming orders include a certificate of conformance.

Quality & Reliability Report 5

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.Control of Inspection, Testing, Measuring and Test Equipment Actel has documented inspection and testing procedures to verify that we meet the specified product requirements. No equipment may be used without a proper record of its most recent calibration.

Control of Nonconforming Products Products that do not conform to specified requirements are identified, segregated, evaluated and properly dispositioned. Reworked products are reinspected in accordance with the quality plan and documented procedures.

Corrective and Preventive Action System Actel takes corrective and preventive actions to eliminate the causes of actual or potential nonconformities to a degree appropriate to the magnitude of the problems and commensurate with the risks encountered. When quality and reliability problems are detected, assignable causes are defined and corrected. Corrective and preventive actions are taken to prevent the recurrence of problems or nonconformities. The results are tracked regularly to ensure that effective corrective and preventive actions are taken.

Control of Handling, Storage, Packaging, Preservation, and Delivery Methods of handling, storing, packaging, preserving, and delivering of products are established and documented. Appropriate handling and storage includes designating storage areas to preserve products pending use or delivery. Methods for authorizing receipt of and dispatch from these designated areas is stipulated and protection is extended to include preservation and delivery to destination. Packaging and marking requirements are documented.

Internal Quality Audit Actel has an established procedure for planning and implementing internal quality audits to verify that quality activities and their related results comply with planned arrangements. These audits are also used to determine the effectiveness of the quality system. Management personnel for the respective areas are responsible for ensuring that any deficiencies found during the audit are corrected in a timely manner 6

Quality & Reliability Report

Sctel Training Training needs are identified and provided to all personnel that perform activities that affect the quality of Actel products. Personnel that perform specific tasks are selected on the basis of their qualifications, which are determined by appropriate education, training, or-experience.

Servicing On-going technical, product, and application support geared towards achieving high levels of customer satisfaction is available.

Statistical Process Control Applications of statistical techniques for controlling and verifying process capability and product characteristics have been identified.

Continuous Improvement Program There is no perfect quality system, and therefore, Actel recognizes the need for on-going product and process improvements. Actel reassesses its quality improvement activities on a regular basis to ensure that its customers are provided with products and services that have a high level of quality and reliability.

Quality & Reliability Report 7

-WCtel

4. Qualification Program Purpose Qualification is a means of verifying that changes in the circuit design, the fabrication process, packaging materials, and/or assembly methods enable the product to meet the specified reliability requirements. In addition, the qualification process is a source of information on the major characteristics of new products and process technologies. Actel's standard reliability qualification programs are described in the following sections, followed by explanations of significant reliability tests. Product reliability has been evaluated on Actel's numerous existing products. Reliability tests are classified by geometry and were conducted on different package types. Descriptions of each test and a summary of relevant data are provided in the following sections.

8 Quality & Reliability Report

-AOcteI Figure 4-1 New Product Qualification (Typical Flow)

Quality & Reliability Report 9

Orctel New Fab Process Technology Newfab process technology requires three wafer diffusion lots for qualification of each wafer foundry. Products can be mixed during qualification as long as data is collected from at least one run of the product with the largest die size.

New Fab Process Technology (Typical Flow)

Three (3) sorted wafer lots, i.e.,

same process, design rule, and architecture Figure 4-2 New Fab Process Technology (Typical Flow) 10 Quality & Reliability Report

Mctef New Package New package qualifications require three package assembly lots for qualification of each assembly site. Assembly lots can be mixed from different fab lots yielded from different fab sites as long as data that is collected for that package is based on the product with the largest die size and highest lead count. A new package is defined as the first member of the package family for Actel.

Ceramic package qualification is per QCI requirement (as defined in Mil-STD-883).

New Package Qualification Flow (Typical Flow)

Three (3) sorted wafer lots, i.e.,

Qualification Proposal same process, design rule, and architecture Ship wafers to assembly. Each wafer lot is assembled with one week interval.

Figure 4-3 New Package Qualification Flow (Typical Flow)

Quality & Reliability Report 11

-- ctel Large Die Qualification Any new product with a die size that is 15 percent (measurement per die side) greater than the qualified product within the same product/process families requires qualification on one lot.

This requirement also applies to package families.

Existing Package When an existing package is transferred to another assembly vendor, one lot is required for each package family (in addition to the reliability and qualification data from the original assembly vendor). Qualification must be done on the largest body size, highest lead count, and largest die size per package family.

12 Quality & Reliability Report

-Actef Existing Package Qualification Flow One (1) sorted wafer lot, i.e.,

same process, design rule, and architecture Figure 4-4 Existing Package Qualification Flow Quality & Reliability Report 13

--0cte1 Table 4-1 Reliability Test Conditions Event "

Test Method Purpose of Test Conditions-

1. HTOL Mil 1015 Determine the effect of high temperature 5.75V1, 1250C, and voltage on device performance 1,000 hours0 days 0 hours 0 weeks 0 months

2. Preconditioning Stress JEDEC-A113 Stress the integrity of the plastic package Appendix A on Test (Plastic Package) through board assembly simulation page 57

3. HAST JEDEC -Al10 Evaluate the moisture resistance of die in 130°C, plastic package 85% RH for 100 hours0.00116 days 0.0278 hours 1.653439e-4 weeks 3.805e-5 months

4. Temperature Cycle Mil 1010, Cond C Accelerate the thermo-mechanical failure 1,000 cycles mechanism of the package

5. Temperature Humidity Accelerate the moisture dependent failure 85°C, 85%RH mechanism of the plastic package Unbiased 1,000 hours0 days 0 hours 0 weeks 0 months

6. Thermal Shock Mil 1011 Accelerate the thermo-mechanical failure

-65°C to 1500 C, (optional for Plastic mechanism of the package liquid to liquid, Package) 15 cycles

7. High Temperature Detect mechanical reliability problems like 150'C Unbiased Storage (optional for bond integrity caused by temperature 1,000 hours0 days 0 hours 0 weeks 0 months Plastic Package) change

8. Solderability Mil 2003 Determine the solderability of the device terminations to simulate the soldering process that will be used in the device application

9. Mark Permanency Mil 2015 Evaluate the marking integrity by using various solvents

10. Lead Integrity Mil 2004 Determine the package lead integrity

11. Physical Dimension Mil 2016 Verify the physical dimensions of the device are in accordance with the applicable procurement document

12. Group D-Hermetic Mil 5005 Ceramic package integrity tests Packages Only

13. LTOL 2 Determine effect of low temperature and 4.0V 1, -55°C (Low Temperature voltage on device performance 1,000 hours0 days 0 hours 0 weeks 0 months Operating Life)

Notes:

I.

3.OV for 0.25pio, 4.OV for 0.351an.

2.

For M2M products only. 3.OV for 0.25prn, 4.OV for 0.35 pin.

14 Quality & Reliability Report

~ctel Table 4-2 Actei's Standard of Quality and Reliability Event Test Method Sample Plan' Accept

of Lots Conditions Criteria Needed

1. HTOL Mi 1015 26 devices/lot 0/78 3

5.75V, 125-C, 1,000 hours0 days 0 hours 0 weeks 0 months 1

2. Preconditioning "Preconditioning" 3

Option #1 or #2 3 Stress Test on page 18

3. HAST JEDEC All 0, 26 devices/lot 0/78 3

130°C, 85% RH for 100 hours0.00116 days 0.0278 hours 1.653439e-4 weeks 3.805e-5 months 2, 3

4. Temperature Cycle Mi 1010, 26 devices/lot 0/78 3

1,000 cycles Condition C

5. ESD Mil 3015 6 units 0/6 3

>2,OOOV 4

6. Latch Up JEDEC 17 6 units 0/6 3

>150mA each I/O with no Latch Up

7. Bond Pull Mil 2011 195 wires/lot 0/195 3

5 units/lot, 39 wires/unit 5

8. Ball Shear 6 wires/unit 0/5 3

5 units/lot 3,

9. Die Shear Mil 2019 45 die/lot 0/45 3

See note 5

10. Solderability Mil 2003 3 units/lot 0/3 2

All leads 5

11. Lead Integrity Mil 2004 5 units/lot 0/225 2

45 leads/unit 5

12. C-SAM 10 units/lot 3

10 units/lot min. 5

13. Mark Permanency Mil 2015 4 units/lot/solvent 0/4 2

4 units/solvent 5

14. X-Ray Mil 2012 45 units/lot 0/45 3

See note 5

15. Package Outline 5 units/lot 0/5 1

See note 5 Check

16. Thermal Shock Mil 1011 26 devices/lot 0/78 3

-65°C to 1501C, (optional for plastic liquid to liquid, packages) 15 cycles

17. Group D tests Mil 5005 There is no information available at this time.

(Hermetic pkgs only)

Notes:

1. May decide to ship at 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months . May also use 150°C, 500 hours0.00579 days 0.139 hours 8.267196e-4 weeks 1.9025e-4 months to replace 1250C, 1,000 hours0 days 0 hours 0 weeks 0 months (can ship at 336 hours0.00389 days 0.0933 hours 5.555556e-4 weeks 1.27848e-4 months @ 150°C). 3.OV for 0.251.m, 4.OV for 0.351pm.

2. 5.OV alternate pin bias for 100 hours0.00116 days 0.0278 hours 1.653439e-4 weeks 3.805e-5 months may be substituted with 1,000 hour0 days 0 hours 0 weeks 0 months THB (85'C, 85%RH) and 96 hours0.00111 days 0.0267 hours 1.587302e-4 weeks 3.6528e-5 months of Pressure Cooker Test (PCT) with sample plan of 26/lot, 3 lots with accept criteria, 0/78.

3. For non-hermetic surface mount packages only.

4. For ESD test, all pins > 2,OOOV with no repeating pins < 2,OOOV. OK to ship if > 750V and corrective action exists for 2,000V.

5. Performed in-line by vendor per lot.

If a package has already been qualified for one product in the same wafer fab and assembly site, quality and reliability test #'s 2, 3, 4, 7-16 do not have to be repeated, unless the new product has a die size that is 15% or more larger than the qualified die.

Quality & Reliability Report 15

-_cteI Table 4-3 Actel's Standard Qualification Requirements for New Products New NewCeramic NewPlastic Test Description Product(s)

New Fab

'Package Package

1. HTOL X1 x

x2

2. HAST X

X1 X1

3. Temperature Cycle x

x X

4. ESD X

X

5. Latch Up X

X

6. Bond Pull X

X X

7. Ball Shear X

X

8. Die Shear X

X

9. Solderability X

X

10. Lead Integrity X

X

11. Mark Permanency X

X

12. X-Ray X

X

13. Preconditioning X

X

14. C-SAM X

X

15. Thermal Shock -Optional (Plastic)

X X

X

16. AC/DC Characteristics X

X

17. Group D X

Notes:

1. For a new product and new fab, three wafer runs are required for qualification. Before qualification is completed, devices may be shipped as pre-production samples. Parts are believed to be good; some testing has been done. All parts must be marked "PP." Customers are advised of part status.

2. If a package has already been qualified for one product in the same assembly site and same fab process, test

Ws 2, 3, 4, 7-17 do not have to be repeated unless the new product has a die size that is 15% or more larger than the qualified die. If there are several packages within a family (same body size, lead finish, and package material), a new family member does not require qualification if:

A product within the same product family in a large die size is already qualified.

There is no change in the package body outline and the lead pitch is not smaller than this family member being qualified.

The distance from the package edge to the die edge is less than or equal to the qualified package family member.

16 Quality & Reliability Report

_ctel Table 4-4 Special Combination Qualification Requirements for Process and Design Changes 0

E

."a C

0-1

<:=

M a--)

0 0

u..

o"'

0 0

0 0C 400 a

TestDesc0ption

=

"a O

o..

1. HTOL X

X X

2.

HAST7 X

X8 X

X8

3.

Temp Cycle X

X X

4.

ESD X

5.

Latch Up X

X X

6.

Bond Pull X

X X

X

7.

Ball Shear X

X X

X

8.

Die Shear X

X X

X

9.

Solderability X

X X

10. Lead Plate Thickness X

X X

X

11. Mark Permanency X

X X

12. X-Ray X

X X

X

13. Thermal Shock (Optional)

X X

X

14. C-SAM X

X X

X

15. AC/DC Char X

X X

16. Sort, FT Yield Analysis X

X X

X

17. Program Yield Analysis X

X X

18. High Temperature Storage X

X X

19. Temperature Humidity -

X X

X Unbiased 85°C/85%RH Notes:

1. Analysis is necessary. Once a wafer fab is qualified for a given die redesign change, other fabs can be qualified by test 18 only (no additional HTOL is necessary).

2. MInor Fab change qualification requires determination by the TRB.

3. Major Process Change, refer to Appendix A of MIL-PRF-38535, and MIL-STD 883.

4. New packages are defined as those that have been qualified for the first time.

5. The biggest package and die size for each family must be used for qualification.

6. A Major Die Redesign change is defined as any change of active device size or design rules. If a mask change is minor such as adjust CD, change E-Test structure, etc. only sort and final test yield are required.

7. May substitute 1,000 hours0 days 0 hours 0 weeks 0 months biased THB (85°C, 85% RH).

8. One lot is required for in-house reliability testing. Use qualification and reliability data from the vendor as supporting information.

9. Only required if I/O buffer is redesigned.

Quality & Reliability Report 17

_ octel Preconditioning Use the following conditions for all PLCC, TQFP, VQFP, BGA and PQFP packages.

l. Bake packages according to the package's dry pack baking requirement.

2. Perform C-SAM.

3. Temperature Cycle @ -55°C to 125°C for 10 cycles.

4. Bake all parts at 125°C for 12 hours1.388889e-4 days 0.00333 hours 1.984127e-5 weeks 4.566e-6 months .

5. Moisture soak all parts @ 30°C/60% RH for 196 hours0.00227 days 0.0544 hours 3.240741e-4 weeks 7.4578e-5 months .

6. Simulate all parts through 3 cycles of JR Reflow with the following profile' :

a. Ingress at 25°C.

b.

Ramp up temperature +6°C/second maximum.

c.

Tbmperature maintained at 125 (+/-25)0 C for 120 seconds maximum.

d.

Time above 180'C for 120-180 seconds maximum.

e.

Time at maximum temperature 10-40 seconds.

f Maximum temperature = 220 + 50C.

g.

Ramp down at 6'C/second maximum.

h.

Perform C-SAM.

7. Subject parts to other reliability tests as appropriate.

Use the following conditions for RQ packages.

1. Bake all parts per the package's dry pack baking requirement.

2. Perform C-SAM 1.

3. Temperature Cycle @ -55°C to 125°C for 10 cycles.

4. Bake all parts at 125°C for 12 hours1.388889e-4 days 0.00333 hours 1.984127e-5 weeks 4.566e-6 months .

5. Moisture soak all parts @ 30°C/60% RH for 48 hours5.555556e-4 days 0.0133 hours 7.936508e-5 weeks 1.8264e-5 months .

6. Simulate all parts through 3 cycles of JR Reflow with the following profile1 :

a.

Ingress at 25°C

b.

Ramp up temperature +6°C/second maximum

c.

Temperature maintained at 125 (+/-25)°C for 120 seconds max.

d.

Time above 180°C for 120-180 seconds maximum

e.

Time at maximum temperature 10-40 seconds.

f Maximum temperature = 220 + 50C.

g.

Ramp down at 6°C/second maximum

h.

Perform C-SAM

7. Subject parts to other reliability tests as appropriate.

I. All temperatures refer to the top of the package and are measured on the package body surface. The devices should be allowed to cool down for a minimnum offive (5) minutes between IR convection.

18 Quality & Reliability Report

_wctel

5.

Quality & Reliability Testing High Temperature Operating Life (HTOL)

The intent of an HTOL test is to operate a device dynamically (meaning the device is powered up with I/Os and internal nodes toggling to simulate actual system use) at a high temperature (usually 125°C or 150°C) and extrapolate the failure rate to typical operating conditions. This test is defined by Military Standard-883 in the Group C Quality Conformance Tests. The Arrhenius equation (Equation 1) is used to calculate the extrapolation:

R = R0

exp (Ea/kT)

Eq. I where R is the failure rate, R0 is a constant for a particular process, T is the absolute temperature in degrees Kelvin, k is Boltzmann 's constant (8.62 X 10-5 eV//K), and Ea is the activation energy for the process in electron volts.

To determine the acceleration factor for a given failure mode at temperature T2 as compared with temperature TI, we derive from the Arrhenius equation:

A(TI, T2) = exp[(Ea/k) * [(1/T1)-(I/T2)}]

Eq. 2 To use the Arrhenius equation, we need to know the activation energy of the failure mode.

Table 5-1 gives the activation energies of typical semiconductor failure modes.

Table 5-1 CMOS Failure Modes Failure Mechanism Activation Energy*

Ionic Contamination 1.0 eV Oxide Defects 0.3 eV Hot Carrier Trapping in Oxide (Short Channels)

-0.06 eV Silicon Defects 0.5 eV Aluminum-Silicon-Copper Electromigration 0.6 eV Contact Electromigration 0.9 eV Electrolytic Corrosion 0.54 eV To evaluate Actel's FPGAs, we program an actual design application into most devices (some units are burned in unprogrammed) and perform a dynamic burn-in by toggling the clock pins at I MHz or higher The designs selected use 85 to 97percent of the available logic modules and 85 to 94 percent of the I/Os. Outputs are loaded with 1.2 to 2.8k Q resistors to VCC. Under these conditions, each unit typically draws a minimum of 100 mA during dynamic burn-in. Most of this current comes from the output loading, while about 5 mA is from the device supply current.

For a 125°C burn-in, this results injunction temperatures of at least 150°C for plastic packages and 145°C for ceramic packages (depending on package type). Because junction temperatures can vary a great deal due to package, product, frequency, design, voltage, and other factors, we use the ambient temperature to calculate failure rates. These are worst case conditions because ambient temperature is always lower than junction temperature, and there is less acceleration Quality & Reliability Report 19

_fctel when extrapolating device hours at lower temperatures. Most burn-in is done at VCC = 5. 75V or VCC = 6.0V for 5.OV devices and VCC = 4.OV for 3.3V devices (for voltage acceleration of the antifuse) and 125°C or 150'C.

As mentioned previously, some units are burned in unprogrammed. To accomplish this, we use internal circuitry that allows us to take advantage of the product's test features to shift commands to the chip serially during burn-in. All internal routing tracks are toggled between OV and VCC. When vertical tracks are at VCC, horizontal tracks are held at OV, and vice versa.

Thus, all antifuses that can connect vertical and horizontal tracks receive a full Vcc stress in both directions. These toggling vertical tracks connect to logic module inputs and outputs when a part is programmed. Finally, a command is sent to the chip to toggle some external I/0 pins between OV and VCC. This dynamic burn-in circuit is the same one used by Actel to screen unprogrammed products to MIL-STD-883 requirements. Since virtually all antifuses receive a full VCC stress, this screen is much more effective in catching unprogrammed antifuse infant mortality failures than is burning in programmed devices, as it only stresses a fraction of the antifuses.

A failure is defined as any device that shows a functional failure, exceeds data sheet DC limits, or exhibits an AC speed drift. Among the parts tested, no speed drift, faster or slower; has been observed within the accuracy of the test setup. Failure rates at 550 C, 70'C, and 90'C were extrapolated by using the Arrhenius equation and general activation energies of 0.6 eV and 0.9 eV Poisson statistics were used to derive a calculated failure rate with a 60 percent confidence level. Poisson statistics are valid for low failure rates and failure modes occurring randomly with time. At 55°C, the calculated failure rate with a confidence level of 60 percent (0.6 eV) was 22 FITs, or 0.0022 percent failures per 1,000 hours0 days 0 hours 0 weeks 0 months . This number was derived from nearly nine million device hours (at 125°C) of data. There were seven total failures out of 7704 tested units representing 134 different wafer lots. There were no infant mortality failures, which would normally occur in the first 80 hours9.259259e-4 days 0.0222 hours 1.322751e-4 weeks 3.044e-5 months of burn-in. Six of the seven failures observed were' due to common CMOS failure modes (gate oxide failure, silicon defects, or open Via). This single antifuse-relatedftailure in nine million device hours at 125'C represents a product antifuse failure rate of significantly less than 10 FITs at 5.5V Table 5-2 0.2 5p High Temperature Operating Life (HTOL)

Number of Failures (Hours)

Product Run #

Package Units 168 500 1,000 2,000

,e-I Z3JUUZ 208 P-l-"urr SX32A T25J002 208 PQFP IOU U

U 80 0

20 Quality & Reliability Report

-wcteI Table 5-3 0.35p High Temperature Operating Life (HTOL)

Number of Failures (Hours)

Product Run #

Package Units 168 500 1,000 2,000 SX16 2ZXR402521 208 PQFP 38 0

0 0

SX16P 2ACT1 41821 208 PQFP 45 0

0 0

SX32 2XZT091468 208 PQFP 43 0

0 0

0 SX16 2ACT110031 208 PQFP 74 0

0 0

0 SX32 2ACT500021 208 CQFP 45 0

0 0

SX16 2ACT1 00081 208 PQFP 81 0

0 0

0 Table 5-4 0.45p High Temperature Operating Life (HTOL)

Number of Failures (Hours)

Product Run #

Package Units 168 500 1,000 2,000 MX04 2XZR24206.5 84 PLCC 29 0

0 0

0 MX04 2ACR23038.3 84 PLCC 30 0

0 0

0 MX16 2XZR25104.1 160 PQFP 26 0

0 0

0 MX04 2ACR23038.3 84 PLCC 45 0

0 0

0 MX36 2ACT1 60221 208 PQFP 27 0

0 0

0 MX04 2ACT1 60021 84 PLCC 77 0

0 0

0 MX36 2ACT363611 256 CQFP 77 0

0 0

MXE4 2ACU040091 84 PLCC 77 0

0 0

0 Table 5-5 0.6p High Temperature Operating Life (HTOL) for RadTolerant SX Devices Number of Failures (Hours)

Product, Run #

Package Units 168 500 1,000 2,000 RTSX16 P02, P03, P04 208 PQFP 81 0

0 0

RTSX16 P05 256 CQFP 77 0

0 0

RTSX16 P04(9931) 208 CQFP 46 0

0 0

0 RTSX32 T6JPO1A (9949) 256 CQFP 76 0

0 0

Table 5-6 0.6p High Temperature Operating Life (HTOL)

Number.of Failures (Hours)

Product Run #

Pakae

.Product n#

.,_Package Units 168 500 1,000 2,000.

1225XL ACP02187.1 100 PQFP 26 0

0 0

1225XL ACQ10102 100 PQFP 56 0

0 0

ACQ07959 ACQ09061 1240XL ACP01117.1 144 PQFP 52 0

0 0

ACN51939.1 1240XL ACP57584.1 84 PLCC 100 0

0 0

1240XL MIX 144 PQFP 56 0

0 0

Failures are attributed to electrical overstress and are not related to Die fabrication.

Quality & Reliability Report 21

_ ctel Table 5-6 0.6p High Temperature Operating Life (HTOL) (Continued)

Number of Failures (Hours)

Product Run#.

Package Units 168 500 1,000 2,000 1280XL ACP212072 160 PQFP 76 0

0 0

ACP1 9329.1 1280XL MIX 84 PLCC 100 0

0 0

3265DX ACP163684 160 PQFP 78 0

0 0

A1415 ACP17300 100 PQFP 100 0

0 0

A1425 ACP122761 100 PQFP 100 0

0 0

A1425 ACP12285 100 PQFP 88 0

0 0

ACP34166 ACP27991 1460BP 25430540 208 PQFP 52 0

0 0

25430550 14100BP 26026670 208 RQFP 27 0

0 0

32140DX ACP33277.1 208 PQFP 75 0

0 0

ACP55730.1 ACP54023.1 32140DX ACP56255.1 208 PQFP 52 0

0 0

ACP56254.1 32140DX ACP540231 160 PQFP 26 0

0 0

ACP56254.1 32140DX 25464510 160 PQFP 26 0

0 0

32200DX 26207340 208 PQFP 29 0

0 0

32140DX ACP562551 208 PQFP 28 0

0 0

1415A ACP17300 100 PQFP 101 0

0 0

32300DX ACQ09069.1 240 RQFP 26 0

2*

0 A1425A UCJ01,02,03 133 PGA 130 0

(1 50-C)

A32100DX ACR50293.1 84 CQFP 80 0

(1 50°C) 32140DX G10854 208C PQFP 26 0

0 0

1280XL ACR53214 160 PQFP 129 0

A1240XL ACR50594.1 144C PQFP 228 0

A1240XL ACR50594.1 144C PQFP 143 0

A1240XL ACR50594.1 144C PQFP 227 0

A1280XL ACT1 0293.1 172 CQFP 80 0

0 0

A32200DX ACT166851 256 CQFP 77 0

0 0

A1280XL ACU166851 176 PGA 76 0

0 0

Failures are attributed to electrical overstress and are not related to Die fabrication.

22 Quality & Reliability Report

Sctel Table 5-7 0.8p. High Temperature Operating Life (HTOL)

Number of Failures (Hours)

Product Run #

Package Units 7168-7 500 1,000 1280XL 24464430 160 PQFP 78 1

0 0

24442620 24381610 1425 JK08, 09,10 133 PGA 140 0

0 0

1425 JK08, 09,10 84 PLCC 135 0

0 0

1425A UCJ01,2, 3 133 PGA 130 0

0 0

1425A ACN32804 133 PGA 130 0

0 0

ACN30805 ACN33807 A1425 UCJ013 100 PQFP 100 0

0 0

1440A JN05 100 VQFP 79 0

0 0

1440A 51940.1 100 VQFP 79 0

0 0

1460A JL-01 208 PQFP 80 0

0 0

1460A JL-01 207 PGA 80 0

0 0

1460A JL-03 208 PQFP 62 0

0 0

1460A JL-06B 207 PGA 65 0

0 0

1460A PC435091 207 PGA 80 0

0 0

PC435092 207 PGA PC435093 207 PGA 14100A 24239130 208 RQFP 51 0

0 0

UCLO1 208 RQFP 25 0

0 0

14100A 25290820 313 PBGA 45 0

0 0

A1460A UCKTO1 207 CPGA 81 0

(1500C)

A32100DX 84 CQFP 80 A14100A UCL049 256 CQFP 15 0

A1460A UCK056 207B PGA 80 0

(1500C, 184 hrs) 1280XL ACT10293.1 721 CQFP 80 0

(1500C, 184 hrs)

RT14100A UCL055 256E CQFP 18 0

A14100A UCL058 256E CQFP 82 0

(1500C, 184 hrs)

Quality & Reliability Report 23

_ctel Table 5-8 1.01p High Temperature Operating Life (HTOL)

Number of Failures (Hours)

Product Runn#

Package,

Units 168 500 1,000 2,000 1010A JG03 68 PLCC 59 0

0 0

0 1010A JG03 68 PLCC 117 0

0 0

0 1010A T124 68 PLCC 74 0

0 0

0 1010A T11104 68 PLCC 107 0

0 0

T11243 T11263 T11297 1010A E01-1 68 PLCC 69 0

0 0

1010A E02-1 68 PLCC 70 0

0 0

1010B T12072857 68 PLCC 400

1.

0 0

T12072858 T12072860 1010B U1G-01 68 PLCC 79 0

0 0

1010B U1G-02 68 PLCC 57 0

0 1010B U9GO1 P 100 PQFP 76 0

0 0

1020A JF01 84 PLCC 25 0

0 0

0 1020A JF01 84 PLCC 15 0

0 0

0 1020A JF02 84 PLCC 44 0

0 0

0 1020A JF02 84 PLCC 41 0

0 0

0 1020A JF04 84 PLCC 77 0

0 0

1020A JF04 84 PLCC 20 0

0 1020A JF14 84 PLCC 58 0

0 1020A JF14 84 PLCC 100 0

V 1020A JF37 84 PLCC 14 1V 1020A JF37 84 PLCC 20 0

1020A JF39 84 PLCC 32 0

1020A JF39 84 PLCC 29 0

1020A JF42 84 PLCC 49 0

0 1020A JF42 84 PLCC 30 0

1

1020A JF66 84 PLCC 33 0

0 0

1020A JF66 84 PLCC 39 0

0 0

1020A JF67 84 PLCC 49 0

0 0

1020A JF67 84 PLCC 45 0

.0 0

1020A TI S#1 84 PLCC 79 0

0 0

1020A E-14 84 PLCC 45 0

0 0

0 1020A E-15 84 PLCC 44 0

0 0

0 1020A E-17 84 PLCC 45 0

0 0

0 1020A JF-207 100 PQFP 129 0

0 0

- Failures are attributed to electrical overstress and are not related to Die fabrication.

24 Quality & Reliability Report

ttel Table 5-8 1.0Qp High Temperature Operating Life (HTOL) (Continued)

Number of Failures (Hours)

Product Run #

Package Units 168 500 1,000 2,000 1020A D1J1815 84 PGA 51 0

0 0

D2B2704 1020A E-01 84 PLCC 45 0

0 0

1020A E-02 84 PLCC 45 0

0 0

1020A E-03 84 PLCC 45 0

0 0

1020A ADK29X 84 PLCC 45 0

0 0

0 1020A ADA72X 84 PLCC 45 0

0 0

0 1020A ADC21X 84 PLCC 45 0

0 0

0 1020A T11130 84 PLCC 223 0

0 0

1020A T11800 84 PLCC 34 0

0 1020A UP-04 84 PLCC 40 0

0 0

UP-05 84 PLCC 40 0

0 0

1010B T15276893 84 PLCC 100 0

0 0

1020B JJ-14 84 PLCC 45 0

0 0

1020B JJ-15 84 PLCC 45 0

0 0

1020B JJ-17 84 PLCC 45 0

0 0

1020B JJ-13 84 PGA 30 0

0 0

1020B JJ-13 84 PGA 80 0

0 1020B JJ-16 84 PLCC 80 0

0 0

1020B U1P-01 84 PLCC 40 0

0 0

1020B U1P-02 84 PLCC 40 0

0 0

1020B JJ-24 84 PLCC 87 0

0 0

1020B EBFJO01 84 PLCC 40 0

0 0

1020B EBFI004 84 PLCC 40 0

0 0

1020B U1 P41 HM 100 PQFP 80 0

0 0

1020B U1P25 80 VQFP 45 0

0 1020B U1P83 80 VQFP 43 0

0 0

U1P25 80VQFP 39 0

0 0

1020B U1P05 100 PQFP 129 0

0 0

1020B U1P209B 84 PLCC 40 0

0 0

1020B U9PO1 100 PQFP 133 0

1 0

U9PO21A 100 PQFP 1020B U9P-004 84 PLCC 47 0

0 0

1020B U9P046 84 PLCC 100 0

0 0

1020B 6085878 84 PLCC 100 0

0 0

1020B U9P128 84 PLCC 100 0

0 0

1020B UP121 84 CQFP 24 0

0 0

1225 UJ-01 100 PGA 80 0

0 0

Failures are attributed to electrical overstress and are not related to Die fabrication.

Quality & Reliability Report 25

Sctel Table 5-8 1.0p High Temperature Operating Life (HTOL) (Continued)

Number of Failures (Hours)

Product Run#

Package Units 168 500 1,000 2,000 1225 UJ-01 100 PQFP 127 0

0 0

A1225 T19028537 84 PLCC 100 0

0 0

1225A U1J-02 100 PQFP 80 0

0 0

A1225A MIX 100 PQFP 32 0

0 0

1240 T13257 132 PGA 7

0 0

1240 T13257 144 PQFP 129 0

0 0

1240 T11045571 132 PGA 38 0

0 0

0 1240 T11053933 132 PGA 55 0

0 0

0 1240 T11053932 132 PGA 36 0

0 0

0 1240 T11220494 132 PGA 90 0

0 0

1240 UI-01 132 PGA 50 0

0 0

1240 UI-03 84 PLCC 80 0

0 0

1240 MIX 144 PQFP 36 0

0 0

1240A E-02,03 144 PQFP 100 0

0 0

1240A E-04 84 PLCC 30 0

0 0

0 1240A U11-26 144 PQFP 80 0

0 0

1280 JH05 176 PGA 15 0

0 0

0 1280 JH06 176 PGA 15 0

0 0

0 1280 JH03(K) 176 PGA 25 0

0 0

0 1280 JH03(SB) 176 PGA 25 0

0 0

0 1280 T11143649 176 PGA 44 0

1*

0 1280 T11143650 176 PGA 44 0

0 0

1280 TI1136307 176 PGA 42 0

0 0

1280 UH-01 176 PGA 26 0

0 0

1280 UH-02 176 PGA 26 0

0 0

1280 UH-05 176 PGA 40 0

0 0

1280 UH-04 160 PQFP 79 0

0 0

1280 UH-10,14 176 PGA 75 0

0 0

1280 ADC18X 160 PQFP 130 0

0 0

1280A EBFJO02 160 PQFP 30 0

1280A EBFJO03 160 PQFP 30 0

1280A EBFJO04 160 PQFP 20 0

1280A U1H-01 160 PQFP 27 0

0 0

0 1280A U1H-02 160 PQFP 27 0

0 0

0 1280A U1H-35 176 PGA 132 0

1280A U1H-18 160 PQFP 80 0

0 0

1280A EWAJ03,4 160 PQFP 134 0

0 0

Failtres are attributed to electrical overstress and are not related to Die fabrication.

26 Quality & Reliability Report

OrcteI Table 5-8 1.0p High Temperature Operating Life (HTOL) (Continued)

.Number of Failures (Hours)

Product Run,#.

'Package Units 168 500 1,000 2,000 1280A U 1H25, 29 84 PLCC 79 0

0 0

1280A U1H235/6 160 PQFP 80 0

0 0

A1020B 103501 84PLCC 124 0

0 0

A1020A UP121 84E CQFP 24 0

0 0

A1280A U1H486 172B CQFP 81 0

0 0

Lots Accelerated at. 1 50C..

Number of.Failures (Hours)

Product Run #

Package Units 184 500 1,000 A1280A U1H83 172 CQFP 45 0

A1280A U1H363 172 CQFP 58 0

A1280A U1H442 176B PGA 81 0

A1020A U1RT01 84B CQFP 80 0

A1280A UIH439 172 CQFP 18 0

A1280A U1H439 172 CQFP 310 0

A1020 U1RT02 84E CQFP 699 0

A1280A U1H551 176 PGA 77 0

Sutittfres ure attriviL' to tctrLIicLLI Ul'erstrcss Uand areC notl etatell to) DJie JUVicaiLUV.

Quality & Reliability Report 27

_AWctel Highly Accelerated Stress Test (HAST)

As in the 85/85 test, units receive an alternate pin bias (5.5V and OV) but are exposed to a higher pressure and temperature environment. Fifty hours of HAST is generally considered equivalent to 1,000 hours0 days 0 hours 0 weeks 0 months of 85/85. HAST testing has gained wide industry acceptance, and Actel currently uses HAST testing in place of both 85/85 and autoclave testing in most qualifications. As summarized, 1899 units from 51 wafer runs have been tested with only one failure, which occurred at 100 hours0.00116 days 0.0278 hours 1.653439e-4 weeks 3.805e-5 months .

Table 5-9 0.35p FPGA Biased Humidity (HAST)

Number of Failures (Hours)

Product Run #

Package Units

100, A54SX32 2ACU211641 329 BGA 81 0

A54SX16 2ACU211341 208 PQFP 84 0

Table 5-10 0.45p FPGA Biased Humidity (HAST)

Number of Failures' (Hours)

Product Run #

Package Units-100 42MX36 2ACT091141 240 PQFP 79 0

2ACT363661 42MX36 2ACT1 80141 272 BGA 76 0

2ACT230231 Table 5-11 0.6p FPGA Biased Humidity (HAST)

Number of Failures (Hours)

Product Run #

Package Units 50 100 1225XL ACP02187.1 100 PQFP 17 0

1240XL ACP01117.1 144 PQFP 31 0

ACN51939.1 1280XL ACP19329.1 160 PQFP 76 0

ACP212072 1280XL ACP33235.1 160 PQFP 76 0

ACP32219.3 1280XL ACQ01 769 160 PQFP 40 0

ACQ03811 ACQ03814 1280XL ACQ05561 160 PQFP 39 0

ACQ05564 ACQ05562 3265DX ACP163684 160 PQFP 40 0

1415 ACP17300 100 PQFP 50 0

A1425 ACP122761 100 PQFP 50 0

28 Quality & Reliability Report

OfcteI Table 5-11 0.6p FPGA Biased Humidity (HAST) (Continued)

Number of Failures Product Run-#

Package

. Units 50 J 100 32140DX ACP54023.1 160 PQFP 26 0

32140DX ACP33277.1 208 PQFP 76 0

ACP55730.1 AC P54023.1 32200DX 26207340 208 POFP 26 0

14100BP 26330340 208 RQFP 26 0

0 32200DX ACQ03818.1 208 PQFP 30 0

1280XL 26084380 160 PQFP 58 0

32140DX 55558.1 208C PQFP 25 0

Table 5-12 0.8p FPGA Biased Humidity (HAST)

Number of Failures.

(Hours).

Product, Run #

Package Units 50 100 1280XL 24464430 160 PQFP 46 0

24381610 24442620 1425 JK8,9,10 84 PLCC 81 0

1425A ACN32804 100 PQFP 80 0

ACN30805 ACN33807 1425A UCJ01,2,3 100 PQFP 80 0

1440A JN05 100 VQFP 45 0

1440A 51940.1 100 VQFP 45 0

1460A JL04A 208 PQFP 80 0

1460A WB24279010 208 PQFP 47 0

14100A 24239130 208 RQFP 14 0

UCLO1 208 RQFP 31 0

Quality & Reliability Report 29

Orctel Table 5-13 1.0p FPGA Biased Humidity (HAST)

'Number of Failures (Hours).

Product Run Package Units Z7507 100 200

-240 1020A T11130 84 PLCC 77 0

0 0

0 T11139 T11210 1020A UlP05 100 PQFP 45 0

0 1020A U1 P41HM 100 PQFP 81 0

0 1020A U1P-209B 84 PLCC 15 0

0 1020B EBFJO01 84 PLCC 44 0

0 EBFI004 84 PLCC 36 0

0 1020B U9P01 84 PLCC 29 0

0 U9P021A 84 PLCC 50 0

0 1020B U9P039 84 PLCC 50 0

0 1020B U9P046 84 PLCC 50 0

0 1020B 6085878 84 PLCC 50 0

0 1225A T16182116 84 PLCC 52 0

0 T16198610 A1020B 103501 84 PLCC 61 0

Table 5-14 Plastic Quad Flat Pack (PQFP) Biased Humidity (HAST)

Number of Failures (Hours),

Product

Run.#

Package Units I 50 100 1020A U1P05 100 PQFP 45 0

0 1020A U1 P41HM 100 PQFP 81 0

0 1280XL 24464430 160 PQFP 46 0

24381610 24442620 1425A ACN32804 100 PQFP 80 0

ACN30805 ACN33807 1425A UCJ01,2,3 100 PQFP 80 0

1440A JN05 100 VQFP 45 0

1440A 51940.1 100 VQFP 45 0

1460A JL04A 208 PQFP 80 0

1460A WB24279010 208 PQFP 47 0

14100A 24239130 208 RQFP 14 0

UCLO1 208 RQFP 31 0

1225XL ACP02187.1 100 PQFP 17 0

30 Quality & Reliability Report

OfcteI Table 5-14 Plastic Quad Flat Pack (PQFP) Biased Humidity (HAST) (Continued)

Number of Failures (Hours)

Product Run.#

Package

,"Units 50 100 1240XL ACP01117.1 144 PQFP 31 0

ACN51939.1 ACP212072.2 1280XL ACP1 9329.1 160 PQFP 76 0

1280XL ACP33235.1 160 PQFP 76 0

ACP32219.3 3265DX ACP163684 160 PQFP 40 0

1415 ACP17300 100 PQFP 50 0

A1425 ACP122761 100 PQFP 50 0

1280XL ACQ01 769 160 PQFP 40 0

ACQ03811 ACQ03814 1280XL ACQ05561 160 PQFP 39 0

ACQ05564 ACQ05562 1460BP 25430540 208 POFP 52 0

25430550 14100BP 26330340 208 RQFP 26 0

32140DX ACP33277.1 208TE PQFP 76 0

AC P55730.1 ACP54023.1 32200DX 26207340 208 PQFP 26 0

32200DX 26207340 208 PQFP 24 0

0 14100BP 26330340 208 RQFP 26 0

0 32200DX ACQ03818.1 208 PQFP 30 0

1280XL 26084380 160 PQFP 58 0

Quality & Reliability Report 31

-AOctl Table 5-15 Plastic Leaded Chip Carrier (PLCC) Biased Humidity (HAST)

Number of Failures (Hours)

Product Run #

Package-Units 50 100C 1020A T11130 84 PLCC 77 0

0 T11139 T11210 1020A U1 P-209B 84 PLCC 15 0

0 1020B EBFJ001 84 PLCC 44 0

0 1020B EBFI004 84 PLCC 36 0

0 1020B U9PO1 84 PLCC 29 0

0 1020B U9P021A 84 PLCC 50 0

0 1020B U9P039 84 PLCC 50 0

0 1020B U9P046 84 PLCC 50 0

0 1020B 6085878 84 PLCC 50 0

0 1425 JK8,9,10 84 PLCC 81 0

1020B U9P046 84 PLCC 50 0

1020B 6085878 84 PLCC 50 0

1240A TI 0094895/6 84 PLCC 48 0

TI 00113137 TI 0013142 32 Quality & Reliability Report

Sctel Temperature Cycling/Thermal Shock These tests check for package integrity by cycling units through temperature extremes. Data was taken for cycles of O°C to 125 0C, -40 0C to 125°C, and -65°C to 150°C. Both programmed and unprogrammed units were placed on temperature cycles.

Table 5-16 Plastic Quad Flat Pack (PQFP) Temperature Cycle I "I I. Number of Failures (Hours)

Product j Run #

Package Units 200 500 1,000 Temperature Cycle: -55*C to 125*C 32104DX ACQ07975 208 TQFP 31 0

0 0

ACQ06716 32140DX ACQ05572 160 TQFP 16 0

0 0

ACQ09703 1460A 2641,0001 208 PQFP 80 0

0 0

1010B U9G042 100 PQFP 25 0

0 Temperature Cycle: -65°C to 150°C 1020A J F-71 100 PQFP 129 0

0 0

1020B U1 P41HM 100 PQFP 80 0

0 0

1020B U1P05 100 PQFP 80 0

0 0

1280XL 25026540 176 TQFP 17 0

0 1280XL 25312500 160 PQFP 76 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 76 0

0 25312480 160 PQFP 1280XL 25312500 160 PQFP 75 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 75 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 74 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 76 0

0 0

25312480 160 PQFP 1425A UCJ01,2,3 100 PQFP 80 0

0 0

1425A ACN32804 100 PQFP 80 0

0 0

ACN30805 ACN33807 1440A JN-02 160 PQFP 80 0

0 0

1440A JN-05 100 VQFP 80 0

0 1

1440A 51940.1 100 VQFP 45 0

0 0

1460A JL-01 208 PQFP 80 0

0 0

1460A 25364430 208 PQFP 45 0

0 0

14100A 24239130 208 RQFP 14 0

UCLO1 208 RQFP 31 0

Quality & Reliability Report 33

Orctel Table 5-16 Plastic Quad Flat Pack (PQFP) Temperature Cycle (Continued)

Number of Failures (Hours)

Product FRun.#

Package Units.

-200 500 1,000 14100A 25371980 208 RQFP 19 0

25364960 208 ROFP 14100A 26026670 208 RQFP 26 0

0 0

1225XL ACP02187.1 100 PQFP 18 0

0 1240XL ACP01117.1 144 PQFP 30 0

0 ACN51939.1 1280XL ACP19329.1 160 PQFP 38 0

0 0

ACP212072.2 160 PQFP 38 0

0 0

1280XL ACP33235.1 160 PQFP 76 0

0 0

ACP32219.3 3265DX ACP163684 160 PQFP 45 0

0 0

1440A 51940.1 100 VQFP 45 0

0 0

1415A ACP212001 100 VQFP 50 0

0 0

1415A ACP17300 100 PQFP 50 0

0 0

1460BP 25430540 208 PQFP 52 0

0 0

25430550 14100BP 26330340 208 RQFP 26 0

0 0

32200DX 26207340 208TE PQFP 26 0

0 0

32140DX ACP33277.1 208TE PQFP 76 0

0 0

ACP55730.1 ACP54023.1 32140DX 26231860 208 PQFP 40 0

0 0

32140DX 26145020 208 PQFP 40 0

0 0

1460BP 26232850 208 PQFP 40 0

32410DX 26272490 208 PQFP 38 0

32410DX 26026660 208 PQFP 52 0

0 0

32200DX 26207340 208 PQFP 48 0

0 0

32410DX 26073180 208 PQFP 39 0

0 0

A54SX16 2ACU241341 208 PQFP 93 0

0 0

2ACU420072 2ACU2224488 34 Quality & Reliability Report

Table 5-17 Plastic Leaded Chip Carrier (PLCC) Temperature Cycle 1

1 1

"Number of Failures (Hours)

Product J

Run#

IPackage J_ Units [ 100 500 1,00 2,000 Temperature Cycle: 00C to 125°C 1010A T115 68 PLCC 125 0

0 0

1010A T124 68 PLCC 176 0

0 0

1010A T11104 68 PLCC 129 0

0 0

0 T11243 T11263 T11297 1020A T11800 84 PLCC 129 0

0 0

0 TI 1859 T12156 Temperature Cycle: -40 0C to 125°C 1010A T11104 68 PLCC 129 0

0 0

0 TI 1243 T11263 T11297 1020A T11800 84 PLCC 129 0

0 0

0 T11859 T12156 Temperature Cycle: -55°0 to 125°C 1020B U9P186 84 PLCC 30 0

0 0

U9P200 1225XL ACQ-MIX 84 PLCC 39 0

0 0

Temperature Cycle: -65 0C to 150°O 1020A JF-71 100 POFP 129 0

0 0

1010A T11104 68 PLCC 129 0

0 0

0 TI 1243 TI 1263 TI 1297 1010B T12072857 68 PLCC 201 0

0 0

T12072858 T12072860 1010B U1G-01,02 68 PLCC 40 0

0 0

1020A T11800 84 PLCC 129 0

0 0

0 TI 1859 T12156 1020A E01 84 PLCC 85 0

0 0

E02 E03 1020A S-1702A,B,C 84 PLCC 144 0

0 0

1020B JJ14-17 84 PLCC 81 0

0 0

1020B U1P-01,02 84 PLCC 40 0

0 0

1020B EBFJO01 84 PLCC 80 0

0 0

1020B EWAI003 84 PLCC 80 0

0 0

Quality & Reliability Report 35

- 7ctel Table 5-17 Plastic Leaded Chip Carrier (PLCC) Temperature Cycle (Continued)

Number of Failures (Hours)

Product Run-#.

Package 1

Units 100-

ý 500 1,000 2,000:

1020B U1P-209B 84 PLCC 15 0

0 0

1020B U9PO21A 84 PLCC 55 0

0 0

1020B u9PO1 84 PLCC 23 0

0 0

1020B U9P039 84 PLCC 50 0

0 0

1020B U9P046 84 PLCC 50 0

0 0

1020B 6085878 84 PLCC 50 0

0 0

1425 JK8,9,10 84 PLCC 83 0

0 0

1240A TI 0113140/1 84 PLCC 56 0

0 0

TI 0094898/9 TI 0094889 A1240A T16163513 84 PLCC 40 0

0 0

T16163521 T16163522 A1225A T19039849 84 PLCC 16 0

0 0

T16182117 Table 5-18

0. 4 5p FPGA Temperature Cycle 36 Quality & Reliability Report

Sctel Table 5-19 0.6p FPGA Temperature Cycle

.Number of Failures (Hours)

.Product R #.

Prdut un, #,

Package,..

Units 200

I 00ý:

1,0007

-55°C to 125*C 1225XL MIX 84 PLCC 39 0

0 0

32140DX ACQ07975 208TE PQFP 31 0

0 0

ACQ06716 32140DX ACQ05572 160TE PQFP 16 0

0 0

ACQ09703 1225XL ACP02187.1 100 PQFP 18 0

0 1240XL ACP01117.1 144 PQFP 30 0

0 ACN51939.1 1280XL ACP1 9329.1 160 PQFP 38 0

0 0

ACP212072 160 PQFP 38 0

0 0

3265DX ACP163684 160 PQFP 45 0

0 0

1440A 51940.1 100 VQFP 45 0

0 0

A1415 ACP212001 100 VQFP 50

.0 0

0 A1415 ACP17300 100 PQFP 50 0

0 0

A14100 26026670 208 RQFP 26 0

0 0

1460BP 25430540 208 PQFP 52 0

0 0

25430550 14100BP 26026670 208 RQFP 45 0

0 0

26330340 32140DX ACP54023.1 160 PQFP 26 0

0 0

32140DX ACP33277.1 208 PQFP 76 0

0 0

AC P55730.1 ACP54023.1 32200DX 26207340 208 PQFP 26 0

0 0

-65°C to 150'C 32140DX 2623860 208 PQFP 40 0

0 0

32140DX 26145020 208 PQFP 40 0

0 0

1460BP 26247840 208 PQFP 40 0

1460BP 26232850 208 PQFP 40 0

3241 ODX 26272490 208 PQFP 38 0

3241 ODX 26026660 208 PQFP 52 0

0 0

32200DX 26207340 208 PQFP 48 0

0 0

3241 ODX 26073180 208 PQFP 39 0

0 0

3241 ODX 26090100 208 PQFP 26 0

0 0

1460BP 26465100 208 PQFP 59 0

0 0

32300DX ACQ09705.1 204 RQFP 25 0

0 0

32140DX 266026660 208 PQFP 35 0

0 0

32140DX 266026660A 208 PQFP 78 0

0 1280XL 25026540 176 TQFP 17 0

0 Quality & Reliability Report 37

--OcteI Table 5-19 0.6 p FPGA Temperature Cycle (Continued)

Number of Failures (Hours)

Product Run-4 Package-Units 200 500 1,000 1280XL 25312500 160 PQFP 76 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 76 0

0 25312480 160 PQFP 1280XL 25312500 160 PQFP 75 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 75 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 74 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 74 0

0 0

25312480 160 PQFP 1280XL 25312500 160 PQFP 76 0

0 0

25312480 160 PQFP 1280XL 25504560 160 PQFP 36 0

0 0

26010580 1425 JK8,9,10 133 PGA 81 0

0 0

1425 JK8,9,10 84 PLCC 83 0

0 0

1425A UCJ01,2,3 100 PQFP 80 0

0 0

1425A ACN32804 100 PQFP 80 0

0 0

ACN30805 ACN33807 1440A JN-02 160 PQFP 80 0

0 0

1440A JN-05 100 VQFP 80 0

0 1

1440A 51940.1 100 VQFP 45 0

0 0

1460A JL-01 208 PQFP 80 0

0 0

1460A JL-01 207 PGA 80 0

0 0

1460A PC435091 207 PGA 80 0

0 0

1460A 25364430 208 PQFP 45 0

0 0

1460A 261,0001 208 PQFP 80 0

0 0

14100A 24239130 208 RQFP 14 0

UCLO1 208 RQFP 31 0

14100A 25371980 208 RQFP 19 0

25364960 14100A 25290820 313 PBGA 78 0

0 0

14100A MIX 208 RQC 24 0

38 Quality & Reliability Report

Table 5-20 1.01p FPGA Temperature Cycle 1..

t Number of Failures (Hours)

Product.

Run Package Units 100 500 1,000 2,000

-0°C to 125°C 1010A T115 68 PLCC 125 0

0 0

1010A T124 68 PLCC 176 0

0 0

1010A T11104 68 PLCC 129 0

0 0

0 T11243 T11263 T11297 1020A T11800 84 PLCC 129 0

0 0

0 T11859 T12156

-40'C to 125'C 1010A T11104 68 PLCC 129 0

0 0

0 TI1243 T11263 T11297 1020A T11800 84 PLCC 129 0

0 0

0 T11859 T12156

-55 0C to 125°C 1020B U9P186 68 PLCC 30 0

0 0

U9P200 1020B U9G042 100 PQFP 25 0

0 0

-65 0C to 150 0C 1010A T11104 68 PLCC 129 0

0 0

0 TI 1243 T11263 T11297 1010B T12072857 68 PLCC 201 0

0 0

T12072858 T12072860 1010B U1G-01,02 68 PLCC 40 0

0 0

1020A T11800 84 PLCC 129 0

0 0

0 T11859 T12156 1020A JF-71 100 PQFP 129 0

0 0

1020A E01 84 PLCC 85 0

0 0

E02 E03 1020A S-1702A,B,C 84 PLCC 144 0

0 0

1020B JJ14-17 84 PLCC 81 0

0 0

1020B U1P-01,02 84 PLCC 40 0

0 0

1020B EBFJO01 84 PLCC 80 0

0 0

1020B U1 P41HM 100 PQFP 80 0

0 0

Quality & Reliability Report 39

__7ctel Table 5-20 1.Op FPGA Temperature Cycle (Continued)

Number of Failures (Hours)

Product, RUn#

Package Units 100

500, 1,000

-,,"2,000 1020B EWAI003 84 PLCC 80 0

0 0

1020B U 1 P-209B 84 PLCC 15 0

0 0

1020B U1 P05 100 PQFP 80, 0

0 0

1020B U9P021A 84 PLCC 55 0

0 0

U9PO1 23 0

0 0

1020B U9P039 84 PLCC 50 0

0 0

1020B U9P046 84 PLCC 50 0

0 0

1020B 6085878 84 PLCC 50 0

0 0

A1225A T19039849 84 PLCC 16 0

0 0

T16182117 A1240A T10094901 144 PQFP 36 0

0 0

T10081338 T10113145 A1020B 103501 84 PLCC 62 0

0 A1240A T16163513 84 PLCC 40 0

0 0

T16163521 T16163522 40 Quality & Reliability Report

ScteI Electrostatic Discharge (ESD)

Causes of ESD Electrostatic energy is static electricity, a stationary charge, that builds up in either a nonconductive material or in ungrounded or grounded conductive material. This charge occurs either through polarization, which occurs when conductive material is exposed to a magnetic field, or through the triboelectric effect, which occurs when two surfaces contact and separate, leaving one positively charged and the other negatively charged. Friction between two materials increases the triboelectric charge by increasing the surface area that comes in contact. A good example is the charge that accumulates when you walk across a nylon carpet.

The discharge occurs when you reach for a door knob or other conductive surface. The types of ESD with which we are concerned fall into the category of the triboelectric effect. In this category, various materials have differing potentials fbr charge. Human hair and nylon have a high positive triboelectric potential. Silicon's negative triboelectrical potential is among the highest. Cotton, wood, steel, and paper have relatively neutral polarity, which makes cotton clothing and steel table tops excellent ESD protective material where ESD problems can be anticipated. The intensity of the charge is inversely)proportional to the relative humidity. As humidity decreases, ESD problems increase. When an object storing static charge comes into contact with another object, the charge will attempt to find a path to ground, discharging into the contacted object. Although the current level is extremely low (less than 0.1 nanoamp), the voltage can be as high as 35kV to 50kV The degree of damage caused by ESD is a function of the size of the charge (which is determined by the capacitance of the charged object) and the rate at which it is discharged (determined by the resistance of the object into which it is discharged). When both are low, the discharge rate will be fast enough to cause damage if the object into which discharge occurs is a semiconductor As capacitance and resistance increase, the discharge rate and risk of damage decreases.

Types of ESD Damage The damage caused by ESD results from the tendency of the charge to seek the shortest path to ground, over-stressing an electrical circuit on that path. There are several different types of damage that result, each of which is typical of specific component technologies and elements.

Some types of damage that can occur during an ESD event are dielectric breakdown, thermal secondary breakdown or junction burnout, and melted metalization.

ESD Protective Measures The development offaster and more complex integrated circuits makes it less likely that the industry will return to thicker oxides and larger junctions. Some complex protective networks use polysilicon resistors that are placed in series with each input pin, and relatively large geometry diodes are added as clamps on the IC side of those resistors. Clamping diodes are also used at the output. These diodes restrict the magnitude of the voltages that can reach the internal circuitry. Protective devices like this have enabled CMOS devices to withstand test voltages in excess of 2kV Quality & Reliability Report 41

OqcteI All Actel products contain static electricity protection circuitry and are tested for sensitivity to static electricity by using the human body model (as described in Mil-STD-883D) (100pF discharged through 1.5k Q). Three positive and three negative pulses are discharged into each pin tested at each voltage level. For inputs and I/Os, these six pulses are applied with three different grounding conditions. Thus each pin receives a total of 18 pulses for each test voltage.

After pulsing, the units are tested on a VLSI tester Leakage currents are measured at OV and 5.0V. Any pin showing more than IpA of leakage is considered a failure. A summary of ESD results for all Actelfamilies is listed below.

ACT 1 Family These devices, which include AIOJOB andAIO2OB, are fabricated onl a 1.0.t process and have been tested to an ESD level of 2,0OOVV ACT2 Family These devices, which include A 1240A, A 1280A, and RTI280A, are fabricated on a 1.0ýt process and have been tested to an ESD level of I,O000V XL Family The A/280XL device is fabricated onl a 0.6jt process and has been tested to an ESD level of 1,500V.

ACT 3 Family These devices, which include AJ425A, RT1425A, A1460A, RT1460A, AI41OOA, and RTI41OOA, are fabricated on a 0.8g process and have been tested to an ESD level of I,O000V A32DX Family These devices, which include A32100DX and A32200DX are fabricated on a 0.6p. process and have been tested to an ESD level of 2,0OOV.

A42MX The MX36 device is fabricated on a 0.45g process and has been tested to an ESD level of 2, 000V A54SX The A54SX32 device is fabricated on a 0.35 t process and has been tested to an ESD level of 2,000 V RT54SX The RT54SX16 device is fabricated on a 0.6gt process and has been tested to an ESD level greater than 2,OOOV except for the FCLK pin, which fails at 2,000/V RH The RH 1020 and RTI020 devices are fabricated on a 1.Opt process and have been tested to an ESD level of 2,0OOV.

The RH1280 device is fabricated onl a 0.8gt process and has been tested to an ESD level of 1,500V.

42 Quality & Reliability Report

AwcteI Latch-Up Latch-up is a well known cause offailure in CMOS circuits. Parasitic bipolar transistors are created by P-channel transistors, N-channel transistors, the N-wells, and the P-substrate. These transistors are connected in a manner that effectively creates an SCR. If a voltage on an external pin forward biases to the substrate, the parasitic SCR can be latched to the on state, thereby creating a low-impedance path between Vcc and ground. A large amount of current then flows through this path. This current will temporarily make the device nonfunctional and may even cause permanent damage.

There are several techniques used by CMOS designers to reduce the chance of latch-up. One of the most common techniques is to use guard rings to isolate P-channel and N-channel transistors. The disadvantage of this method is that it requires additional silicon die area.

Another method is to use EPI wafers to achieve low substrate resistance, which reduces the chance of triggering latch-up. in geometries greater than 0.45pom, Actel uses both guard ring and EPI wafers to reduce susceptibility to latch-up. With the reduced susceptibility of O.45pm and smaller geometries, Actel uses guard rings consistently and often in combination with other reduction techniques in its designs.

The latch-up test method is defined by JEDEC Standard No. 7. Each I/0 pin on a tested device is forward biased in both directions (to VSS and VCC) by forcing negative and positive currents ranging from +/-50mA to +/-400mA in +/-5OmA increments. Following each stress, the device Icc is measured. If the current exceeds the data sheet limit of lOmA the unit is rejected. The unit is also functionally tested to confirm full spec operation.

Nine units, three units from three different wafer lots, are tested to qualify each Actel product.

Testing is done at room temperature as well as at a worst case temperature of + 125°C. All I/Os and power supplies are tested. To date, all products pass a minimum of 25OmA.

Radiation Hardness A programmed ONO antifuse makes a connection between an upper layer of polysilicon and an N+ diffusion on the bottom. This connection is very similar to a buried contact used in some MOS processes because the SXfuse is between M2 and M3. Many other programmable logic products such as RAM, EPROM, and EEPROM, rely on a stored charge to make their connections. This stored charge can be susceptible to degradation from radiation exposure. The Actel antifuse makes a hard contact and does not rely on a stored charge. As a result, Actel products have superior radiation tolerance when compared with products that use a stored charge.

Quality & Reliability Report 43

_ 0cteI

6.

SPC Data Wafer Fabrication DICD FICD TLCOX Thickness FLDOX Thickness Bottom Oxide Thickness Top Oxide Thickness Nitride Thickness Passivation Oxide Thickness

7. SPC Data Assembly Wafer thickness Wafer Saw Kerf Width DI Water Resistivity DI Water Pressure Wire Bond Pull Strength Wire Bond Ball Shear Strength Mold Temperature Mold Package Centering Lead Plating Thickness Lead Plating Composition Lead Form External Width Lead Coplanarity 44 Quality & Reliability Report

~cteI

8.

Reliability: FIT Rate Failure Rates and Mean Time to Failure Component failure rates are commonly expressed in Failures in Time (FITs). A FIT is one failure in one billion device-hours. To calculate failure rates for the high temperature operating life test, the acceleration factor is calculated. The acceleration factor is the ratio of the in-stress failure rate to the failure rate during use conditions. For dry life, the acceleration factor is calculated using the Arrehenius model with a 0.7eV activation energy. The acceleration factor is determined by the junction temperature in use, the junction temperature in stress, and the activation energy characterizing the failure mechanism.

To calculate the junction temperature, you must determine the power dissipation (PD),

measured in watts. PD(watts) = Icc - VCC. Obtain the temperature rise by using the following equation:

PD(watts)

Oja(°C)/watt = ???

where Oja is the package thermal resistance, and then adding the temperature rise to the ambient temperature.

TJ7C) = Ta(C) + PD - Oja(°C/watt)

Eq. 3 Eq. 4 Table 8-1 FIT Rates Time Period Q2'96 Q1'97 02'97 -Q3/Q4'97 Q1'98 Q2'98 Q3'98 04'98,Q1'99 02'99 03'99 Q4'99 Q1'OO 1p (FITS) 13.87 13.37 13.29 12.9 10.9 10.3 10.3 10.3 10.3 10.3 10.3 9.43 9.43 0.8V (FITS) 20 19 19 18.5 16.6 16.6 15.5 15.5 15.5 15.5 15.5 15.5 14.77 0.6p (FITS) 18 12.11 10.87 5.75 5.68 5.36 5.36 5.36 5.36 5.36 5.36 5.01 4.85 0.45p (FITS) 90.4 30 25 25 23.53 23.53 23.53 16.36 0.35p, (FITS) 96 335 5

29.2 29.2 22.51 RTSX 0.6p (FITS) 145 145 74.6 74.7 36.18 0.25p (FITS) 145 145 74.6 74.7 112.33 Figure 8-1 FIT Rates Quality & Reliability Report 45

A9.

Process Flow Comparisons for HiRel Devices*

0 CS CS Production Flows"

, I Commercial Industrial' 1

Mi!. Temp.'- 2 Class.BIO' 3

I RT/RP RT/RP1"4 RH' 5 Class S'-1 I

(Mi.lStd-883, Test Method)

Flow Plastics On Flow 1

Flow Flow E FIw VQ Flow (Reference),

Fiont-End Assembly Processes Wafer Lot Acceptance 3 N/A N/A N/A N/A SEM Report 3.1 Not Required Required (min.

(WLA, TM5007)

(Need step coverage waiver)

(Via plug)

Step Cvg 30%)

Wafer Lot Total Dose N/A N/A N/A N/A Lot Specific Data Guaranteed Guaranteed (TID, TM 1019)

(not guaranteed)

(300 kRad)

(lot specific)

Die Visual Inspection Condition B Comm. 3 Condition B Condition A Condition A (2nd Optical, TM 2010) 2.1 Die Adhesion Test Lot Acceptance Lot Accept.

Lot Acceptance Lot Accept.

Lot Acceptance (Stud Pull, TM 2027) 4 (Die Share)

(minimum 3 units/ lot)

(3 units/lot)

Destructive Wire Bond Lot Acceptance Lot Acceptance Lot Acceptance Lot Accpt. 5 Lot Accpt.

100%

Pull Test (4 units/lot, 10 wires/unit minimum)

(2 units each @

Non-Destructive (TM 2011, Condition D) setup & every 2 setup & lot (TM 2023) hrs.)

completion)

Internal Visual Inspection Condition B Comm.

Condition B 100%

100%

(3rd Optical, TM 2010)2.1 Condition B Condition A Condition A Customer Pre-Cap Source N/A N/A N/A N/A Optional 6 Optional Inspection (TM 2010)

Serialization N/A N/A N/A N/A Optional Required Required Resistance To Solvents Lot Acceptance Lot Acceptance Lot Acceptance Lot Acceptance Lot Acceptance Lot Acceptance Lot Acceptance Lot Acceptance (Mark Permanency, TM2015)

Temperature Cycle 7 N/A N/A N/A 10 cycles 10 cycles 10 cycles 50 cycles 10 cycles (TM 1010)

Condition C Condition C Condition C Condition C Condition C Constant Acceleration N/A N/A N/A Condition D (only CQ84 requires condition E)

Condition D/E (Centrifuge, TM 2001)8 (Direction Y1 only)

Particle Impact Noise N/A N/A N/A N/A Optional Condition A Condition A Detection (Condition A)

(PIND, TM 2020)

Fine & Gross Leak Test QA Samples N/A QA Samples Required N/A N/A (TM 1014)

Radiography N/A N/A N/A N/A Optional 1 view 1 view 1 view (X Ray, TM 2012)

(1 view, and RP (RP waived) waived)

This data is also available on the Actel Website under HiRel.

Production Flows' Commercial Industrial1.'

Mil. Temp.1"2 Class B/Q'3 RT/RP RT/RP1"4 RHl1s1 class s (Mil-Std-883, Test Method)

Flow Plastics Only2..

Flow Flow B/Q Flow E Flow VO Flow (Reference)

Back-End Electrical Testing/Screening Processes Electrical Test Required Required

@ Room Temperature (100% testing per Actel spec., including TM5005 Group A Subgroups 1,7, & 9)

(Commercial Test)

QC Monitor Sample per Wafer Lot (Per Actel Specification)

N/A (Programming)

Pre Burn-In N/A N/A N/A N/A N/A Required Required Required Read & Record (R&R)

(TO test)

Dynamic Burn-In N/A N/A N/A 80 hours9.259259e-4 days 0.0222 hours 1.322751e-4 weeks 3.044e-5 months @ 1500C 240 hours0.00278 days 0.0667 hours 3.968254e-4 weeks 9.132e-5 months @ 12500C 240 hours0.00278 days 0.0667 hours 3.968254e-4 weeks 9.132e-5 months @ 125 (TM 1015)

(Cond. D, Accelerated BI)

Condition D 00 Post Burn-In (Interim)

N/A N/A N/A N/A N/A Required Required Electrical Test (100% testing per Actel spec.,

@ Room Temperature including TM5005 Group A Subgroups 1, 7, & 9)

Post Burn-In (Interim)

N/A N/A N/A N/A N/A Required Required Required Read & Record (R&R)

(T1 test)

Delta Calculation N/A N/A N/A N/A N/A Required Required (Per Actel SMD)

Percent Defective Allowance N/A N/A N/A N/A N/A N/A

< 5% overall, N/A (PDA, TM 5004) and _ 3%

functional (T1 only)

Static Burn In N/A N/A N/A N/A N/A Cond. C Cond. C Cond. C (TM 1015) 72 hours8.333333e-4 days 0.02 hours 1.190476e-4 weeks 2.7396e-5 months at 144 hours0.00167 days 0.04 hours 2.380952e-4 weeks 5.4792e-5 months at 72 hours8.333333e-4 days 0.02 hours 1.190476e-4 weeks 2.7396e-5 months at 150 0C 12500 150 00 Post Burn-In N/A N/A N/A Required Required Electrical Test (100% testing per Actel spec., including TM5005

@ Room Temperature Group A Subgroups 1 & 7)

Post Burn-In N/A N/A N/A N/A N/A Required Required Required Read & Record (R&R)

(T2 test)

Delta Calculation N/A N/A N/A N/A N/A Required Required (Per Actel SMDs)

Percent Defective Allowance N/A N/A N/A PDA < 5% overall

_5 5% overall,

_ 5% overall,

< 5% overall, (PDA, TM 5004) and _ 3%

and*< 3%

and*_< 3%

functional functional functional (T2 only) 0b RP 4

0r 0*

,Production Flows' Commercial idstrial Mil Temp.

Class BI/13 RT/RP RT/RP' RH

.. Class S1 1 (Mil-Std-883, Test Method)

Flow low I

E Flow VQ Flow (Reference),

Final Electrical Test N/A N/A Required Required

(@ -55 0C) 2.2 (100% testing per Actel spec., including TM5005 Group A Subgroups 3, 8b, & 11)

Temperature Test N/A N/A N/A N/A N/A N/A Included 9 N/A Read & Record (R&R)

(T2 test)

Final Electrical Test N/A 0.1% AQL Required Required

(@ +1250C) 2.2 Sample Test (100% testing per Actel spec., including TM5005 Group A Subgroups 2, 8a, & 10)

@ +850C Temperature Test N/A N/A N/A N/A N/A N/A Included 9 N/A Read & Record (R&R)

(T2 test)

GA Electrical Test N/A 0.1% AOL 0.1% AOL Required 5.2 N/A N/A

@ Room Temperature 2.2 Sample Test Sample Test (100% testing per Actel spec., including TM5005 Group A Subgroups 1,7, & 9)

Fine & Gross Leak Test 10 N/A N/A N/A N/A N/A Required Required (TM 1014)

External Visual Inspection Per Actel Specification Only Required Required Required Required Required (TM 2009)

Radiation Latch-Up N/A N/A N/A N/A Generic data only Required (TM 1020)

(tested on initial product qualification)

Quality/Technology Conformance inspection (QCIITCI, TM5005)

Group A 11-1 N/A N/A N/A In-line group A testing is performed on 100% of Waived per 116 / lot devices at all 3 temperatures Mil-PRF-38535 Appendix B11-1.1 Group B 11.2 N/A N/A N/A Group B test for Class B Group B.1-4 for Generic data Group B test for Class S, Class S (8.5 & B.6 optional)

Group C 11.3 N/A N/A N/A Generic Generic Generic Generic Generic Group D 11.4 N/A N/A N/A Generic Generic Generic Generic Generic Group E 11.5 N/A N/A N/A N/A Lot Specific TID Test Only1151 RHA 11-5 2 Required (No Guarantee)

Qualified Lot Specific (b

Sctel Notes:

1. Production Flows:

All screening tests listed in the table are performed on 100% of products except those specified as Lot Acceptance or QA Samples.

1. 1 Both Industrial and Class S flows are for reference only, and are not offered in ceramic packages.

1.2 Military Temperature flow is offered in both ceramic and plastic packages (see note I/ for mil-temp plastic devices).

1.3 Class B and Class 0 process flows are identical and meet the requirements per Appendix A MIL-PRF-38535.

Since Actel has been QML certified by DSCC since February 1998, all new SMD devices are assigned with level Q SMD part number.

1.4 Extended flows (Eflow) meet the requirements per MIL-PRF-38535 Appendix A for class S, with the exceptions shown on the above comparison table between Eflow and Class S.

1.5 RH VO Flow is the production flow used for Actel RHI020 and RH1280 devices. It meets all the requirements in appendix B of MIL-PRF-38535 except the lot specific TCI. It has the Class V level screening, but without the lot specific TCI tests, therefore, both RHI020 and RH1280 SMD part numbers are assigned as Q level only.

2. Plastic-molded packages are offered in 3 application temperature ranges:

Commercial (OYC to +70"C), Industrial (-40'C to +85"C), and Military (-550C to +1250C).

2. 1 For all plastic-molded packages, both second and third optical visual inspection are based on A QL 0.65% sampling plan with 100% re-inspection iffailed sampling plan. Visual inspection criteria are based on vendors' internal specifications, which are generally based on, but not necessary in full compliance with MIL-STD-883, TM2010, Condition B, Internal Visual Inspection.

2. 2 Commercial devices are 100% electrical tested at room temperature only.

Industrial devices are 100% electrical tested at room temperature, and 0. 1% A QL sampling test at +85C. No testing at -40 "C, which is guaranteed by design.

Military temperature devices are up-screened from commercial devices with 100% burn-in (only when required by customers) and 100% temperature tests.

Guarantee for moisture sensitivity on plastic devices are:

" Level 3: PLCC, PQFP, TQFP, VQFP, and BGA packages.

" Level 4: RQFP with exposed heat sink.

CQFP and CPGA are hermetic packages, which are not subjected to moisture sensitivity issues.

3.

Wafer Lot Acceptance (WLA)

3. 1 SEM inspection (TM2018) is waived for devices with via plugs, which include:

RH (1.0/0.8g) devices, XL and DX (0.6Rt) devices, MX (0.45 t) devices, A54SX (0.35A) devices.

Other than the above devices, waivers are required for reduced step coverage that don't meet the 30% minimum requirement per TM2018 section 3.7.2. These devices are:

ACT I and ACT 2 (1.0p) devices, ACT3 (0.8pt) devices, and RT54SX (0.6 PI) devices.

- A CT 1, ACT 2, ACT 3 device families, typical minimum step coverages are >14% (including barrier metal).

RT54SX device family, typical reduced step coverages are between 4% to 10%, but much more when barrier metal is included.

Quality & Reliability Report 49

_ octel

4. Only a minimum of 2 units is used for die attach stud pull and destructive wire pull per each assembly lot prior to 9/30/99.

5. E-flow RTdevices produced at Kyocera SCA will perform 100% destructive wire pull oil setup units.

However, E-flow RP devices produced at Space Electronics Inc. (SEi) will perform only 30%

destructive wire pull on setup units due to the very low through-put of their semi-automatic wire bonding machines.

6.

Precap CS! requires special assembly build to allow scheduling for customer precap CS! dates.

Minimum order quantity will be required to start a custom assembly lot. Actel may refuse customer precap CSI due to an already high inventory position. The customer can always purchase extra units and perform DPA as a substitute for the precap CS! requirement.

7. For the Temperature Cycling Test, all devices except RH devices perform 10 cycles only. This still meets the QML requirement.

8.

Constant acceleration tested on devices with CQ84 packages are condition D only for each assembly lot prior to 9/30/99.

9.

For RH devices, Read and Record is not required at -55"C and + 125('C per mil-spec. They are performed as a preference of LMSEC (Lockheed Martin Space Electronics and Communications, Actel vendor for RH device production).

10. The second Fine & Gross Leak Test is to be completed as the final screening step after the completion of all electrical tests.

11. Quality/Technology Conformance Inspection (QCI/TCI): All QCI/TCi (Group A, B, C, D, & E) tests are performed per MIL-STD-883 Method 5005 or MIL-PRF-38535.

11. 1 Group A electrical tests are lot specific with a sample size of 116/lot or 100% iffewer than 116 units.

11. 1. 1 Actel TRB approved the removal of the end-of-line group A electrical tests at all 3 temperatures starting 12/15/99.

Actel has already implemented in-line group A tests at final electrical tests for all 3 temperatures, which are done on 100% of the devices at tighter limits, therefore, eliminating the redundant end-of-line group A testing will improve process efficiency without affecting the device quality and reliability. The Actel in-line group A testing complies with MIL-PRF-38535, Appendix J, section J.3.11 Inline TCI Testing (option 2).

11. 1.2 Group A can be waived for QML line per MIL-PRF-38535 Appendix B, which is done at LMFS for RH device production.

11. 1.3 Starting 12/15/99, QA electrical testing on 100% of devices is also implemented after the group A electrical testing are eliminated to ensure devices are not damaged due to test setup at hot and cold tests.

11. 2 Group Bfor Class E and Class V includes 1000 hrs life test and thermnal/mechanical test.

Group Bfor class B devices are performed for class B devices. Group Bfor class S devices are performned for E-flow, however, only B. I to B.4 are pemformned on each assembly lot. B.5 1000 hrs life test and B.6 thermal/mnechanical test are only performed when customer requests the test and pays for the cost. Assembly in-line process monitoring data can be used as part of the group B data.

11. 3 Group C is performed once every 4 quarters for each wafer fab technology plus one quarter of extension time.

50 Quality & Reliability Report

_ actel 11.4 Group D is performed once every 6 months for each assembly foundry plus 10 weeks of extension time. RP devices are produced only when needed at very low run rates, so group D is perf.irmed only when customer requests the test and pays for the cost.

11.5 Group E RHA TCO tests:

11. 5.1 Group E test data for RT/RP devices are performed on test samples only. All RT/RP devices have TID (TMIO19) data done on all wafer lots.

11. 5.2 Group Efor RH devices are performed on the RHA qualification lots only.

12. Die business for all die are 100% inspected per MIL-STD-883, Method 2010, Condition B.

Quality & Reliability Report 51

Mctel

10. Customer Process Change Notification (PCN) Flow Foundry/Wafer Change Proposal Notify Actel TD I1 Document Control I Send to customers File 52 Quality & Reliability Report

_ctel

11. Return Materials Authorization (RMA) Process An Actel RMA form is completed by a customer; an Actel sales representative, or a distributor and sent to an Actel customer service representative (CSR). A CSR receives and reviews the RMA request. The CSR then enters the RMA request information with a reason code into the J.D. Edwards (JDE) database.

If the RMA request is approved, an RMA number is issued and a hardcopy is faxed to the customer and to the Actel sales representative or distributor. A copy of the approved RMA form is filed in Customer Service.

An RMA administrator reviews the parts and information upon receipt. The parts are dispositioned, accepted and the customer or distributor is credited.

RMA information is recorded in the JDE database and is traceable by referencing the RMA number

?Notifies it?

Customer/

No Distributor (es ormation in son Code IMA # to istributor CRS Faxes Hardcopy of Approved RMA to Customer/Distributor CRS Files Hardcopy with RMA Information In Customer Service 1

10- Go to next page Figure 11-1 RMA Flow Quality & Reliability Report 53

-4cteI Return To Customer/

Distributor Figure 11-1 RMA Flow (Continued) 54 Quality & Reliability Report

--:cteI

12. Failure Analysis (FA) Process An application engineering (AE) or a CSR receives a FA request from a customer, an Actel sales representative, or a distributor. The AE evaluates the case. If the FA request is accepted, the AE issues a case number for tracking and records failure descriptions.

An FA/RMA administrator receives the parts and forwards them to Product Engineering for failure analysis. The failures are analyzed, cause is determined and, if necessary, corrective action is initiated. Upon completion, a failure analysis report is distributed to AE, QA, CSR, and the sales representative or distributor. A copy of the report is forwarded to Document Control for filing.

Quality & Reliability Report 55

Orctel No No Assign Case #. Complete Customer Information Section of the FA Form RMA/FA Administrator Delivers Parts and Files to PE PE Completes FA and Distrubutes FA Report to AE, CSR, QA, Sales Reps.

Corrective Action Initiated, If Necessary.

Figure 12-1 FA Flow 56 Quality & Reliability Report

Sctel A. Actel and the Antifuse-A Technical Backgrounder Introduction Through the years, the design of digital logic circuits has evolved from working with small-scale integrated circuits (ICs) containing discrete gates to use of large-scale and very-large-scale ICs (VLSI) containing many thousands of gates. A number of commonly-used functions became available in the form of high-density circuits. Yet designers still retained the need to use small-scale ICs, even discrete gates, to solve interface problems and to implement their unique designs. The advent of the field-programmable gate array (FPGA) encapsulated the design flexibility provided by small-scale ICs into a high-density circuit.

The applications for FPGAs are legion. Wherever a design uses a substantial amount of small-and medium-scale ICs there exists the potential for an FPGA to provide a faster, more compact, more reliable solution. FPGAs also excel in new designs, where VLSI alternatives do not exist and the cost of custom ICs is prohibitive. Where complex designs must undergo minor updates to match changing market demands, where designs must be initiated without final specifications in hand, or where production volumes are too low to amortize a custom circuit's setup costs, FPGAs have a home.

The market for FPGAs is substantial and growing. In 1993 the total market for FPGAs and other high capacity programmable logic devices (HCPLDs) exceeded $539M. Dataquest forecasts put the market at $2124M in 1998, representing a compound annual growth rate of 32%. Indeed, the market has attracted a number of vendors, each touting its architecture and technology as the best solution to the needs of logic designers.

Actel Corporation entered the programmable logic market in 1988 with the shipment of itsfirst FPGA. The company's products now include the ACT I, ACT 2, 1200XL, and A CT 3 logic families that span 1,200 to 10,000 gates in density. All are based on the company's multi-patented channeled array architecture and the PLICE (programmable low-impedance circuit element) antifuse.

An antifuse, as its name implies, is like a fuse in reverse. The antifuse begins as a high-impedance (essentially open) circuit element and changes to a low-impedance connection when subjected to a programming voltage. The change is irreversible and highly reliable.

Actel's channeled array architecture uses the PL1CE antifuse to great advantage. The array comprises horizontal rows of logic blocks alternating with channels of pre-defined interconnect tracks segmented into varying lengths. The input and output ports of each logic block connect to vertical tracks that span several logic rows and interconnect channels. The vertical and horizontal tracks are insulated from one another but at each crossover lies an antifuse. When programmed, the antifuse connects the two tracks togethem: Selectively programming the antifuses will create a circuit path between one logic block and another. (See Figure A-I.)

Quality & Reliability Report 57

_ 40ctel Modules q

Unprogrammed Programmed A

Antifuse eN 0-

_j

.1 11 Horizontal Track Modules Vertical Track Horizontal Control Figure A-1 The network of horizontal and vertical interconnect tracts in the ACT family allows arbitrary and flexible interconnections among logic blocks. All speed-critical interconnections can be accomplished programming only two antifuses. Most other connections in the design use two or three antifuses, but never more than four. The result is a device that lets designers utilize in excess of 80%, and in many applications, 100% of the available logic blocks before all available routing channels are taken. And that routing is flexible enough that CAE tools can achieve 100% automatic placement and routing. These levels of utilization and routability are comparable to conventional gate arrays of similar size.

The PLICE antifuse is an integral part of this architecture and helps it to be fully scaleable. The antifuses reside entirely within the interconnect channels and are smaller than the space from one track to the next. Thus, the antifuses interconnects occupy no additional die area. Furthel; they are small enough that improvements in process technology that shrink line spacing won't crowd the antifuses.

The synergy created by the combination of architecture and antifuse technology has allowed Actel to extend its methodology over four generations of parts. The product line now includes a breadth of parts that satisfy a variety of designer's requirements. For example, the ACT 3family offers the highest peiformance and highest pin-to-gate ratio available in high capacity programmable logic today. The A 1440A 4000-gate device can provide serial communications and pipelined datapath designs with clock speeds up to 250 MHz. Devices such as the A 1240XL 4000-gate FPGA can achieve up to 60 MHz overall system operation with 16-bit pre-scale counters that operate at 130 MHz. And for high-volume applications, the ACT I family provides the lowest cost production FPGAs available.

As a result, Actel is among the fastest-growing FPGA companies. Actel has risen to rank among the top 5 suppliers of CMOS programmable logic.

58 Quality & Reliability Report

__A7cteI Antifuse vs. Memory-Based Programmable Logic When it was founded in 1985, Actel sought the best long-term solution to the needs of high-performance programmable logic. It considered a variety of alternatives, examining various antifuse structures. Actel chose to pair an antifuse interconnect scheme with a gate-array-like architecture in order to achieve the highest possible circuit density and, consequently, lowest cost onl a per-gate basis.

Two kinds of gate array structures exist: channeled arrays and channeless sea-of-gates arrays.

The channeled array divides the silicon into strips of logic blocks interspersed with channels containing metal tracks. The sea-of-gates structure uses a myriad of small logic blocks (gates) that cover the silicon, In both cases a network of metal traces provides potential pathways for carrying signals to and from the logic blocks. In the channeled array, the traces within the channels can carry signals alongside the logic. A second layer of metal traces, insulated from the channels and logic blocks, can carry signals across the logic. The sea-of-gates array uses three insulated metal trace layers, two of which run at right angles and the third layer is used to connect the logic blocks. In either case a route from one logic element to another lies along a combination of traces within the two layers, but the traces aren't connected, yet.

A programmable gate array offers the user a means of selectively connecting trace segments in the two layers to form complete circuits between logic elements. The methods used to provide that connection include both memory-driven transistor switches and physical-change structures. With memory-driven interconnections, an EPROM or RAM cell provides a signal that controls a pass transistor When turned on, the transistor provides a signal path between the trace segments it bridges. When off, it isolates the two. By programming the memory cells, the user establishes logic circuits.

Physical-change structures, on the other hand, use an interconnection element that will be physically altered during the programming process. The alteration is permanent, eliminating the need for a memory circuit. Two types of such interconnection elements are possible: the fuse and the antifuse.

The fuse is a familiar structure: a conducting metalfilament that is destroyed when subjected to excessive heat or current, creating an open circuit. Fuses have been used for years as programming elements for memories and simple programmable logic. They are ill-suited to FPGAs, however, because of the many potential connections.

A fuse-based programmable gate array (PGA) would need to start out with all possible connections among the logic elements already made. The user then would remove all the unwanted connections in order to leave the pattern desired. Because a programmed gate array typically uses only 2% of its possible connections, this is rather like building a box by hollowing out a large block of wood-highly inefficient. Fuse-based PGAs can be implemented for factory programming, however, using a laser to cut the unwanted fuses.

Quality & Reliability Report 59

~ctei In contrast to the fuse, the antifuse is a non-conducting circuit element that becomes conducting following application of a programming voltage and current across its terminals. Configuring an antifuse-based FPGA, therefore, requires programming only those connections that are desired, leaving the others alone. You only build the walls you need for your box.

Of all these structures, the antifuse represents the most efficient use of die area. The memory cells needed for memory-based interconnect occupy considerable silicon area. An SRAM cell, for example, needs at least 3 transistors in addition to the pass transistor for the connection.

Further; the pass transistors have to be relatively large to get high performance. This multitude of large transistors occupies more space than the traces alone need. The result is either a relatively large die or limits to the number of interconnections per chip.

An antifuse structure is much more compact. Antifuses typically consist of a thin insulating layer between contact points that begins conducting under application of high voltage, typically 12-20V Once the insulation starts conducting, the antifuse's terminals melt together and form a permanent conducting channel through the insulation. That channel is typically a tenth the size of the tracks being connected. Thus, the antifuse can occupy the space between metal traces, taking up no additional die area. This allows the antifuse to be placed at every potential connection point without affecting the die size.

The antifuse FPGA does lose some chip area because it needs on-chip high-voltage programming circuits. These circuits reside on the chip's edges, however; rather than at each interconnect junction. Thus the die area occupied by the high-voltage drive transistors does not restrict the interconnect density achievable in the rest of the chip, unlike the transistors in a memory-based FPGA. Furthem; as semiconductor processes scale to smaller feature sizes and allow higher gate capacity devices, the relative area occupied by the high-voltage circuits decreases.

In addition to the die area advantages,. the antifuse provides a connection with lower resistance and capacitance than the pass transistors. Lower resistance and capacitance translates into smaller propagation delays, resulting in faster overall circuits.

Antifuse Technology The antifuse concept dates back to at least 1951, when it was considered for use in memories.

The basic antifuse is a thin insulating layer between conductors that gets altered (programmed) by the application of high voltage. The alteration is non-volatile, i.e., it remains after removal of the voltage. Once the change has occurred, a low-resistance path exists between the conductors.

The nature of that path is determined by the type of antifuse structure used. At present, two types of antifuse are commercially produced: the amorphous silicon antifuse and dielectric antifuse.

The amorphous silicon antifuse uses a non-crystalline form of silicon between the conductors, which are typically metal. Under high voltage a section of that amorphous silicon undergoes a phase change and atomsfrom the metal layers it separates migrate into the silicon material. The 60 Quality & Reliability Report

Mctel result is a thin conducting filament composed of a complex mixture of silicon and metal. (For details, see "Appendix A-The Structure of Antifuses" on page 66.) The size and resistance of the filament is dependent on the amount of programming current that flowed during its creation.

This structure has been investigatedfor years and has presented a number of technical hurdles.

To keep within reason the programming voltage needed, the amorphous layer must be thin.

Early attempts to create these thin layers either required processes too costly for high-volume production or resulted in significant thickness variation because of process equipment limitations. The consequence was a history of devices with unpredictable performance. Only in the last 3-4 years has process technology beens sufficiently accurate to control the amorphous silicon thickness.

A more persistent problem with some amorphous silicon antifuses has been their response to high-current pulses. The programmed antifuses sometimes revert to a high-impedance state due to cracking or a phenomenon called read disturb. The result is that the antifuse's resistance jumps, which will change the corresponding logic circuit's propagation delays and may even look to.the logic like an open-circuit. This reversion tends to be self-healing; normal logic-high voltages are sufficient to reprogram the disturbed antifuse. However; there is no guarantee that the node containing the disturbed antifuse will see a logic-high voltage again, once the change has occurred. Thus, the tendency to self-heal is not a reliable antidote. Instead, the FPGA design must limit the current flow through the antifuse to avoid stressing the filament.

The other antifuse type, the dielectric antifuse, uses oxide (glass) as the insulating layer Application of high voltage creates multiple conducting filaments which are prone to self-healing. (See Figure A-2.)

Polysilicon Oxide ONO LaeF Oxide Figure A-2 Actel solved that problem with its patented PLICE antifuse structure. Ihstead of using a single oxide layer, the PLICE antifuse uses a sandwich of oxide, nitride, and oxide (ONO). The ONO layer lies between a polysilicon conductor and a heavily-doped n+ diffusion region of the base silicon wafer Under the programming voltage, the ONO sandwich melts and the base wafer grows an epitaxial "bump" into the polysilicon in the shape of a dome. Growth of the bump shatters the ONO layer, allowing diffusion of the substrate n+ into the polysilicon to form a low-resistance path.

Quality & Reliability Report 61

_ Wctel The bump typically is lOx taller than the ONO layer thickness, preventing any possibility of reinstating the oxide barrier The bump's size also makes the structure tolerant of current-induced stresses. Thus, the PLICE antifuse can safely handle much higher currents than can amorphous silicon. If anything, the high currents would increase the bump's size, strengthening the connection.

Although the PLICE antifuse uses the base silicon as part of its connection between metal layers, it does not steal any die area from the logic circuits in a channeled gate array. The PLICE structure is small enough to fit in the space between metal traces in the channel.

Evolution Antifuse Alternatives Low resistance and capacitance values are among the primary attributes of a good programmable connection for logic. The need for low resistance comes from its interaction with both the connection's capacitance and the parasitic capacitance that occurs in the metal interconnection network and the input structures of logic gates.

The greater the capacitance in a circuit, the more drive current the circuit requires in order to quickly shift logic states. However, the connection's resistance attenuates the drive signal, restricting the amount of current available to change logic states. The combined effect of this resistance and capacitance is to slow the propagation of electrical signals through the circuit.

This slowing, in turn, limits the clock frequency the logic can use. Keeping the connection's capacitance and programmed resistance low minimizes the problem.

Comparing antifuse alternatives solely on the basis of capacitance and typical programmed resistance, however, is to take a near-sighted view. There may be other factors limiting the circuit's clock speed. One such factor is extendability, how well the antifuse structure works over a range of IC sizes. Another is scaleability, how readily the structure shrinks as process lithography improves. The key to creating a useful product is finding an optimum combination of'allfactors.

Consider, for example, the current-carrying capacity of an antifuse structure. Amorphous antifuses, as already described, risk being damaged by too great a current. Thus, an FPGA using amorphous antifuses must be designed to avoid current spikes. Yet current spikes are common in digital circuits. Circuit capacitance and logic switching speed determine the size of those spikes. Therefore, the amorphous-antifuse FPGA must place limits on clock edge rate based on the circuit's capacitance.

One prominent contributor to circuit capacitance is the metal interconnect track. Its capacitance is a function of its length; the longer the track, the greater the capacitance. As the array size gets larger, then, the amorphous-antifuse FPGA must either reduce circuit speed or limit track length to keep current spikes under control. Reducing circuit speed is an obvious disadvantage. Limiting track length is also a disadvantage, however, because it reduces the user's ability toftilly utilize the available gates. Gates widely separated cannot be used in the same circuit.

62 Quality & Reliability Report

_'Mctel The physical layout of an antifuse can also put a limit on the FPGA's ability to scale down as semiconductor processing achieves smaller circuit sizes. A via-type antifuse for example, typically used with amorphous silicon, runs into problems at smaller geometries. To create a repeatable antifuse, the fabrication process must lay down a uniform, controlled thickness of antifuse material. Placing material in a well, as occurs when creating a via between metal layers, results in thinning at the well's corners, as shown in Figure A-3. That thinning is difficult to control, reducing the repeatability of the antifuse layer thickness. The thinning becomes more prominent as the well gets smaller Thus, the via structure for an antifuse is difficult to scale reliably, reducing the opportunity to benefit from process lithography improvements.

Figure A-3 The PLICE antifuse has neither of these limits. The programmed connection is tolerant of current pulses, so is able to handle large circuits without the need to reduce clock speeds or restrict track lengths. The PL1CE structure is planar, not well-like, so thinning is not'prominent.

The result is controlled, repeatable connection.

Another factor to consider is cost. The amorphous-silicon antifuse has the advantage that it can reside between two metal layers. Placing the antifuse between metal layers allows the FPGA to use a sea-of-gates architecture, thereby devoting most of the silicon to logic circuits rather than reserving an area for interconnect channels. The result is a smaller, therefore cheaper, device for a given gate count.

While it is possible to place a PLICE antifuse between two metal layers, the needed metal-poly-ONO-poly-metal sandwich requires too many processing steps. The added processing cost would outweigh the size-reduction savings. A channeled architecture is the most cost-effective match to the PLICE structure.

The cost advantage afforded by a sea-of-gates architecture is of no value without a reliable antifuse, however No one cares that the designer saved a few dollars when the customers start complaining about failed equipment. Evaluating the reliability of an antifuse is an involved task.

Simple burn-in tests aren't adequate; the design must pass tests that accelerate its probable failure modes. Such tests include voltage stress and temperature stress of both programmed and unprogrammed antifuses. The PLICE antifuse has proven its reliability to be less than /0 FITs Quality & Reliability Report 63

Sctel (failures in time; 0.0001%/1000 hours) over 8 million device hours (125YC) of testing. That's equivalent to a device lifetime greater than 40 years. Other antifuse structures have yet to prove similar reliability levels.

Numerous additional factors need consideration when evaluating antifuse structures. Table A-I summarizes several factors and their significance.

Table A-1 Factor

- Significance, Leakage Current Because there are many antifuses on a chip, leakage currents can amount to a consid-erable power consumption. A 10 nano-Ampere leakage current in each of the typical 750,000 antifuses on a large FPGA would waste 7.5 mA.

Programming Voltage The higher the voltage and current needed, the larger the drive transistor must be and and Current the greater the chip area occupied by programming circuits.

Range of Programmed A predictable, narrow range for the resistance values of programmed antifuses allows Resistance accurate timing estimates during simulation and repeatable performance in production.

User Benefits of Actel's Technology Actel has conducted ongoing research into antifuse technology since its founding. In addition to developing its PLICE antifuse, the company has investigated a variety of other structures, including metal-to-metal PLICE, metal-to-metal amorphous silicon, and single-oxide dielectric.

It has also developed and patented both channeled array and sea-of-gates FPGA architectures.

It has picked and chosen from those alternatives based on four user benefits: cost, performance, extendability, and reliability.

The PLICE antifuse coupled with the channeled array architecture represents the most cost-effective design available. The antifuse structure allows a smaller die than equivalent memory-based FPGAs and does not need external memory devices to maintain its programming during power loss. The antifuse's small size also allows the chip to provide extensive routing resources, yielding 85% to 95% utilization of the array's logic blocks. This utilization efficiency allows designers to put more circuits into the smaller devices.

The extensive routing resources also reduce the risk of making logic changes. Once an initial design is complete, FPGA pinout patterns get cast in copper by the printed-circuit board design.

An FPGA with limited resources, however, may not be automatically routable to the same I/O pinl pattern following a logic change. Designers must then either change the circuit board design (a step FPGAs were supposed to help avoid) or spend time hand-routing the FPGA. The ACTfamily's abundance of routing resources avoids such problems.

Compared to SRAM and EPROM memory-based devices, the PLICE antifuse offers lower resistance and capacitance, thus, greater circuit speeds. The PLICE also provides a programmed resistance within a narrow range, making circuit operation predictable and repeatable. The predictability makes for more accurate simulations, allowing users to catch timing bugs early on. The repeatability lets designers to use tighter timing tolerances and wring maximum performance out of the FPGA.

64 Quality & Reliability Report

Sctel While the amorphous-silicon metal-to-metal antifuse and sea-of-gates architecture looks promising, Actel's research has shown that the programmed link is fragile under over-current conditions. Such conditions occur frequently in normal operation, making the field reliability of amorphous antifuses questionable. High circuit speeds and large array sizes increase the likelihood of over-current failure, limiting the speed and size attainable with an amorphous antifuse.

The PLICE antifuse has proven its reliability over many millions of device hours. Once programmed, the structure is highly resistant to damage from current spikes. It does not undergo any form of self-healing, so its programmed resistance remains stable over its expected 40-year+ lifetime. The result is an FPGA that provides predictable, repeatable, consistent performance over a system's product life.

Future Directions in Antifuse Technology The evidence indicates that the PLICE antifuse, coupled with Actel's patented channeled-array architecture, represents the best combination of cost, performance, and reliability among today's FPGA architectures. Building on that foundation, the company has extended its designs to a 0.6-micron process and brought that process on line at three foundries. The PLICE structure benefits from this by scaling in both size and effective speed. Actel plans to soon introduce additional device families based on ONO and the channeled array architecture.

Actel continues to investigate all alternatives, however, to keep providing designers with the best FPGAs possible. The sea-of-gates architecture with a metal-to-metal antifuse has great potential, yet Actel's extensive antifuse research casts doubts on the reliability of existing amorphous silicon antifuses. The company's answer has been to develop a new generation of metal-to-metal antifuse.

Actel's development of a sea-of-gates device began as early as 1990. By 1991 it had patented a sea-of-gates architecture. But Actel's quest for a reliable metal-to-metal antifuse, involving many teams developing alternative approaches in parallel, lead the company to abandon traditional simple via amorphous silicon by 1992.

That quest has been fruitful, however The company has developed a metal-to-metal (M2M) antifuse that solves the problems encountered with amorphous silicon. Built from a proprietary combination of materials, Actel's M2M uses a planar structure rather than a via, so corner thinning, and the resulting manufacturability and reliability concerns, does not become a problem at smaller scales. It achieves a leakage current about one-third that of amorphous silicon, a capacitance 25% less, and a cell size 25% smaller That, coupled with M2M's smaller cell size, promises to allow higher densities at lower cost in Actel's FPGAs. Further, the M2M antifuse's reliability in the face of current surges will allow the development of large, fast arrays where amorphous silicon must slow down to protect against damaging noise spikes Quality & Reliability Report 65

Ofctei Nor is Actel standing still. The company vigorously pursues research into antifuse technology and FPGA architectures. It is committed to continual product improvement in both capability and reliability.

Appendix A-The Structure of Antifuses An antifuse possesses a deceptively simple basic structure. It is a thin layer of insulating material sandwiched between two conductors, forming an open circuit. With the application of a programming-voltage pulse, the insulator melts and forms a conducting path instead. The path remains intact when the voltage pulse ends; a new connection exists.

Although the concept is simple, creating an effective antifuse structure in an integrated circuit is a complex task. Actel was ihefirst company to bring an antifuse-based device to market. Few others have been able to follow. "

Actel's antifuse, called PLICE (programmable low-impedance circuit element), uses polysilicon as one of its conductors, and a diffused n+ region as the second conductor Each conductor connects to one of the metal layers (MI, M2) that route signals through the FPGA. A sandwich of oxide, nitride, end oxide (ONO), 120A thick, separates the two conductors (See Figure A-4).

Poly Figure A-4 In its unprogrammed state, the ONO layer provides a resistance of > 100 mega ohms.

Application of a 16V pulse causes the dielectric layers to melt, allowing current to begin flowing across the ONO layer The current flow stimulates epitaxial crystal growth from the n+

layer into the polysilicon, shattering the ONO layer Excess dopant from the n+ layer migrates into this crystal. When the programming pulse ends, the antifuse cools. leaving a hemispherical 66 Quality & Reliability Report

-- ctel crystalline dome between the two conductors (See Figure A-5). A programming current of 5 mA is sufficient to produce a connection with a nominal 6003/4 resistance. A programming current of 15 mA creates a 1003/4 connection.

Before Programming Polysilicon Oxide ONO Layer I

Oxide After Programming Oxide ONO Layer I

Polvsilicon Figure A-5 Because it uses a diffused n+ region as one of its conductors, the PLICE antifuse needs to be fabricated on top of a silicon layer The most economical place to locate the PLICE antifuse, then, is on the same base layer as the active circuit elements. It is possible to fabricate a PLICE-style antifuse between metal layers using polysilicon between the metal layers and the antifuse. The added process mask steps, however; make this structure economically unattractive.

Quality & Reliability Report 67

_ ctel An antifuse structure that does comfortably fit between metal layers is the amorphous antifuse.

This antifuse structure uses non-crystalline (amorphous) silicon as the insulating layer Between the metal and the amorphous silicon lies a layer of barrier metal. The barrier metal prevents the metal layers from migrating into the silicon under normal operating voltages (See Figure A-6).

Metal2 Barrier Metal Amprphous Silicon Metal 1 Figure A-6 Application of a 15V programming pulse causes a phase change within the amorphous silicon.

A filament of crystalline silicon forms between the metal layers. That filament is a mixture of silicon, the metal-layer material, and the barrier-metal material. Its precise electrical and mechanical characteristics depend on the materials involved and the amount of current that flowed during the filament's formation. A current of 25 mA is generally needed h form a low-resistance connection, typically 80-1003/4.

Once formed, the filament is subject to stresses as current passes through it. Depending on the material mix used, that stress can cause the filament to crack or to electromigrate if the current too great. The result is a jump in resistance of the programmed antifuse. This tendency for resistance shifts puts limits on what the amorphous silicon antifuse can reliably achieve as a circuit element in an FPGA.

Appendix B-The Hidden Cost of Reprogrammability On the surface, reprogrammability may appear to be a no-lose feature in design. The same device can be used time and again rather than using up a new device every time a specification change occurs or a design error is found. Unless reprogrammability is required as part of the system-level design, however, the feature's hidden costs can substantially outweigh its apparent benefits.

Designers that utilize reprogrammable devices have developed a trial-and-error design philosophy. They try out their design, then examine its output signals to figure out what's happening. Based solely on these signals, they make an educated guess at what went wrong, and try again. Each attempt requires that they enter design changes, compile the design into a 68 Quality & Reliability Report

__octel program map, program the device, and check it out. For complex designs this cycle repeats many times. The trial-and-error approach becomes even more difficult and time-consuming if the design uses asynchronous logic. Even seemingly minor changes to an asynchronous design can cause sections that were working to now fail.

Use of a reprogrammable device eliminates the material cost of the trial-and-error approach.

The time spent debugging, modifying, and repeating the cycle represents a hidden cost, however, in man-hours and schedule delays. Engineering budgets typically run about $3000/week; successful companies such as 3Com and Hewlett-Packard have estimated that a week's schedule delay cuts $30,000 from a product's lifetime profits. Yet, because it eliminates the apparent cost, reprogrammability encourages the trial-and-error approach and corresponding wasted time.

A similar situation existed during the early days of microprocessor-based designs. Because the programmable processor replaced fixed-logic circuits, it eliminated the apparent cost of correcting design flaws on PC boards. Users now know how expensive fixing software by trial-and-error can become. As a result, a host of tools like in-circuit emulators exist to take the guesswork out of correcting errors.

The equivalent for programmable logic design is the simulator. By using a simulator, designers have access to what's happening inside the design. By providing full modeling of the design, including postroute timing, simulation enables the designer to adopt a debug methodology that is quicker, more controllable, and less frustrating than the trial-and-error approach. Being able to see exactly what is wrong reduces the number offix-and-retest cycles required to achieve a working design. Surveys indicate that fewer than five cycles are needed to debug a design when designers use simulation.

Some bugs, of course, don't show up until actual circuit testing of FPGAs with external elements may have been less complete. To prevent trial and error debugging at this stage, Actel provides built-in test circuitry in its FPGAs. The Actionprobe diagnostic circuits allow the user to route internal signals to the output pins of the FPGA for examination. This probing capability provides 100% observability of internal nodes in response to system stimuli and thereby reduces design iterations.

Simulation and test circuits help eliminate guesswork, but they require designers to learn new tools. That's time and money spent that is not obviously contributing to the project's completion and many designer won't bother when they don't have the specter of expended one-time programmable (OTP) parts to frighten them into it. The weeks saved by encouraging better debug techniques more than justify the 5 or so devices that get consumed.

There are other hidden costs associated with using reprogrammable parts. RAM-based FPGAs, for instance, need an external non-volatile memory to retain configuration data when power is absent. That device has a price, and the board area it occupies has a cost. Further, the design becomes more complex because it needs to suspend operation following power up to allow time for the FPGA to get reconfigured.

Quality & Reliability Report 69

Reprogrammable FPGAs also tend to be more expensive than antifuse FPGAs for a given gate count. The internal memory structures that give an FPGA reprogrammability occupy a significant portion of the device's area. That extra area makes the reprogrammable part much larger than a Actel 's antifuse-based OTP FPGA, adding die cost.

The extra area occupied by those memory structures also compels memory-based FPGA manufacturers to restrict routing resources to reduce the associated memory penalty. With restricted routing, a design may not efficiently utilize the FPGA's available logic. That, in turn, may force designers to use a size FPGA larger than expected, further increasing cost.

Restricted routing can also add to the cost of design changes. Once a design has been committed to a PCB, users don't want internal logic changes to alter the FPGA 's pinout. Yet a device with sparse interconnect resources may not be routable to a set pinout following a logic change. Worse, the new logic design may be routable, but suffer performance problems because of changes to internal circuit delays.

The antifuse-based Actel parts offer abundant routing with little area penalty because the antifuse structures fit into the otherwise unusable space between routing traces. The result is better than 85% logic utilization, allowing designs to crowd into the smaller FPGAs, and 100%

automatic routing.

Many of reprogrammability's hidden costs are prices paid by manufacturing for a feature that's only useful during design or in systems that need to be reconfigured frequently. Thus, unless the system needs dictate reprogrammability (and few do), the savings in parts cost during debug is spent again and again during production. That expense adds to the time expended in the trial-and-error approach that reprogrammability promotes. The sum is a feature that, in most cases, costs far more than it is worth.

70 Quality & Reliability Report

OrcteI B. Oxide-Nitride-Oxide Antifuse Reliability Steve Chiang. Roger Wang, Jacob Chen, Ken Hayes, John McCollum, Esmat Hamdy, Chenminq Hu*

Actel Corp.

955 E.

Argues Ave. Sunnyvale, CA 94086 Phone: (408)739?1010

Department of Electrical Engineering and Computer Science U.C. Berkeley, Berkeley, CA 94720 Abstract

Compact, low-resistance oxide-nitride-oxide antifuses are studied for TDDB, program dis-turb, programmed antifuse resistance stabil-ity. and effective screen.

ONO antifuse is superior to oxide antifuse. No ONO antifuse failures were observed in 1.8 million accel-erated burn-in device-hours accumulated on 1108 product units.

This is in agreement with the lI/E field acceleration model.

Introduction Field programmable gate arrays has been a fast growing field only recently[l].

The key to their configurability is the development of a programmable interconnect element. This element should have small

area, low post programming resistance, and be reliable.

Many known interconnect elements have been used, including SRAMs,

EPROMs, and EEPROMs.

Problems encountered using these elements are: large area, high resistance, or ineffi-cient utilization due to circuit complexity.

The antifuse

approach, however, has some unique and attractive features. Since it is only a

two terminal

device, the area required is small, and the simple two termi-nal resistor structure allows simple and efficient routing schemes[2].

The programmed antifuse has very low resistance.

It was found that oxide-nitride-oxide (ONO) anti-fuses have a lower and tighter resistance distribution than that of oxide antifuses (Fig.

1).

The choice of antifuse material has further improved both the yield and the reliability over that of oxide antifuses. In addition, ONO is highly radiation resistant.

Initial evaluation results indicate that products containing ONO antifuses can with-stand 1.5 million rads[3].

The technology and performance characteristics of the ONO antifuse has been previously described[4].

In this paper, we will report the reliabil-ity characterization of the ONO antifuse.

We will discuss three different type.

of antifuse reliability. The first is that the unprogrammed antifuse has to survive a 5.5V 40 year operating condition. The second is that during programming, all unprogrammed antifuses are subject to a momentary stress of half the programming voltage (Vpp/2).

The programming yield is required to match or exceed PAL yields which are in excess of 99%.

The third is that programmed antifuses should have a very low resistance, which will not increase in value over the life of the part. As will be shown below, the unpro-grammed antifuse is reliable, well in excess of the 40 year lifespan, the programming yield is excellent, and the programmed anti-fuse is not subject to any measurable elec-tromigration.

The weakest link in the technology is not the antifuse, but typical CMOS process limitations.

Antifuse Structure The ONO antifuse is sandwiched between N+

diffusion and N+ poly-silicon gate to form a very dense array with density' limited by metal pitches (Fig.

2).

A thin layer of oxide is thermally grown on top of the N+

surface, followed by LPCVD nitride, and the reoxidized top oxide.

The target electrical thickness of the combined layer is equiva-lent to 9nm of silicon dioxide.

TDDB of Unprogrammed Antifuses at 5.5V For the sub 10 nm ONO thickness, time-depen-dent-dielectric-breakdown (TDDB) reliabil-ity over 40 years is an important consideration. The very first task in deter-mining the feasibility of the antifuse was to examine its TDDB reliability.

Typical electrical field and temperature accelerated tests were done in order to extrapolate the dielectric lifetime under normal operating conditions. Based on the oxide study[S].

it was reported that there may be different field dependencies of lifetime in high field

(>6MV/cm) and in low field (c5MV/cm) regimes.

In the case of ONO antifuses, the 5.5V operating field is already over 6MV/cm.

She extrapolated data from the high field regime was therefore assumed accurate.

This assumption was later confirmed with device burn-in data.

Field Acceleration (Z vs 1/Z model for 0-0) 200X200 um2 (O.04mm2) area capacitors were packaged and then stressed at different voltages.

ONO thickness ranging from 8nm to 9.5nm were studied. The test splits and sam-ple sizes are summarized in Table

1. The TDDB distribution at each voltage condition is shown in Fig. 3.

In the literature, the oxide intrinsic life-time has been observed to have an exp(I/E) dependence, which is explained mainly with the Fowler-Nordheim tunneling mechanism 163.

oxide Log(I) curves and lifetime Log(t50) curves exhibit a linear function of lI/E behavior, on the other hand, nitride Log(l) has been shown to follow the Frenkel Poole behavior (1E)

[7].

Log(I) of ONO is not a linear function of lI/E (Fig. 4a).

Rather, it Quality & Reliability Report 71

__cteI more eral an E closely follows E (Fig. 4b).

Also, sev-studies have fitted lifetime of ONO to model[8,9].

Nevertheless a careful examination 4f our data revealed:

that TDDB lifetime of ONO follows the 1/E model (Fig.

5) better than the E model (Fig.

6). This is in agreement with conclusions from one study[10],

but in contradiction with others which did not examine the fit between date and the I/E model [8,9].

Based on our observation, we.

found that the E model can fit the data well over 4

to 5 orders of magnitude of time span.

However, as time span increases to 7 orders of magnitude, the E model is clearly inadequate (Fig.

6).

Since there is no theoretical basis for ONO to follow the 1/E model or the E model, we:

tried a statistical approach to find out which model can best fit the data. First, the data is fitted to different field depen-dent models of exp(En) with n

ranging from:-l.5 to 1 at 0.5 intervals.

Then the correlation coefficient is compared for dif-ferent models in Fig.

7.

The residual com-parison is shown in Fig.

8.

Again, the E model (n=l) turns out not to be a good fit for the data. The best fit appears to be n =

-0.5 or -1. This seems: to suggest that ONO behavior is similar to oxide (n=-l).

But,.the addition of nitride (n=0.5]

has changed the n to between -0.5 to -1. Which of the two exponents:,

n=-0.5 or -1, should be used may depend on the ONO processing conditions. The difference between extrapo-lated lifetime based on these two models is not nearly as dramatic as the choice between E and 1/E.

At 5.5V, the difference in the extrapolated lifetime between n, -0.5 and -1 is one order of magnitude in time.

On the other hand, the difference between -0.5 and

-1 is 5 orders of magnitude.

In the subse-quent analysis, we will use 1/E model exclu-sively for simplicity.

The conclusion reached will not change much if the 1/1E model were to be used.

Besides the 0.04mm2 area capacitor data, we also did a TDDB study on single antifuses (3.2um2) and ACT 1010 product antifuse arrays (0.36mm2).

Results are shown in Fig.

9.

Again, the data follows the I/E model well for all different area sizes.

Temperature Acceleration The temperature effect on the 0.04mm2 ONO area capacitor lifetime is shown in Fig. 10.

The activation energy as a function of the electrical field is shown in Pig.

11. A field dependent activation energy has been reported for oxide TDDB lifetime, as well.

For the 5.5 volt lifetime

estimate, the activation energy is close to 0.9eV (I/E model).

Using this estimate and the product TDD8 defect distribution (Fig.

12), the 1%

failure lifetime at 5.5V is well over 40 years.

The projected product antifuse fail-ure rate (Containing 100K to 200K antifuses) is less than 50 FITS at 125 0 C.

Program Disturb and Screen During programming all antifuse electrodes are precharged at a given voltage, Vpre.

To program the antifuse, its poly-silicon elec-trode is raised to Vpp while its N+ diffu-sion is grounded.

The unselected antifuses are subjected to the stress of either Vpre to. ground or VPP to Vpre for an average of 100 times the single antifuse programming time.

Usually the Vpre is set such that tress is approximately VPP/2.

If defective unselected antifuses fail (become pro-grammed) due to this stress, they will show up as programming failures. These defective antifuses can be screened out at wafer sort by a 1 second stress at 10 voles (10V/ls).

This screen is done twice during sort. The first lOv/ls (FS-l) screens out the defec-tive dielectric distribution.

The second 1OV/ls stress (FS-2) simulates the percent yield loss during programming.

In Fig.

13, it shows a typical wafer trend on the fail-ure rate of both first and second stress.

The 10 run averages of FS-2 is 0.3%.

This suggests that the programming failure loss due to antifuse defects after the screen should be less than 0.3%.

Unlike floating gate EPROMs and EEPROMs ONO defects can be easily screened out with a voltage stress as. described above. This is one more advantage of the antifuse structure as a programming element.

Once an antifuse has passed the voltage screen at sort, it is very reliable. Based on either 1/E or 1/lE

model, the 10v/Is stress is equivalent to a stress time at 5.5v well over 40 years. We have calculated the equivalent product fail-ure rate at 5.5v as a function of the FS?2 screen yield loss. It shows that for an Fs?2 of 0.5-. the equivalent FlTs at 5.5V 1251C is less than 50, which is consistent with the results mentioned at the end of the pre-vious section.

Programmed Antifuse Reliability Once the antifuse is programmed and forms a low resistance path, the resistance should remain low.

In the case of oxide, it is a

known fact that they are susceptible to self healing

[11] or an increase in resistance with time. This is not the case for ONO as will be shown in the following section.

A four terminal Kelvin structure was used for the reliability study (Fig. 14).

A con-stant mA current, which is much larger than the operating current, was passed through the antifuse at 250 c (through terminals A, B) while the voltage across the antifuse was monitored between terminal. A and B. A typi-cal voltage vs time graph is shown in Fig.

15.

A sudden increase in voltage indicates that an open circuit has formed.

Prior to 72 Quality & Reliability Report

__cteI that, there is no significant change in the voltage across the antifuse indicating that the resistance remained low.

Next, electric continuity measurement and scanning electron microscopy (SEM) were done on the Kelvin structure.

It was found that the antifuse resistance still remained low when measured from the other two untreated terminals C and D. This is the case for all samples tested under this condition, SEM analysis showed that the open circuit was related to the metal to poly contact elec-tromigration failure (Fig. 16).

The activa-tion energy (based on 2500C and 2000C data) for the contact electromigration is l.leY, which is in agreement with typical values obtained from contact

electromigration failures

[12].

The extrapolated lifetime of contacts in these circuits under normal operating conditions is well in excess of 40 years.

The real lifetime of a programmed antifuse itself is yet to be determined.

High Temperature Product Burn-in Life Data In previous sections, it was demonstrated that the extrapolated ONO antifuse lifetime follows the l/E model instead of the E-model.

Product burn-in data supports this conclusion.

1108-units (including

PROMs, ACT1010 and ACT1020) containing an average of about 100K antifuses per unit, about 5%

of which were programmed, underwent dynamic burn-in at 1251C and 5.5V with roughly an accumulated 1.8 million device hours.

No antifuse failure has been observed while two CMOS circuit failures have been observed and identified in the peripheral circuitry. This data is consistent with the failure rate projection based on I/E extrapolation. while the E model extrapolation based on TDDB test data would have projected 90 unit failures (out of 1108 units) due to ONO antifuses.

Conclusions We have investigated three reliability aspects of the ONO antifuses. During opera-tion, the lifetime of the ONO antifuse is well in excess of 40 year. at elevated tem-peratures.

It has been further demonstrated that the E model is not adequate for life-time extrapolation.

Results indicate that 1/E is better choice.

The key to successful extrapolation is that data should span over even orders of magnitude in time.

Based on the 1/E model, the extrapolated lifetime is well over 40 years at 5.5v.

To screen out the programming yield loss due to breakdowns of defective unselected antifuses, a screen was developed. This is not a yield limiting factor in the typical process as the yield loss due to the screen on the average is 1-.

After the screen, the programming yield is higher than 99t.

The reliability of pro-grammed ONO antifuses was also studied. It was found that the lifetime is limited by the contact electromigration. not by the ONO antifuse.

In

addition, the resistance remains low throughout the test indicating the antifuse resistance does not increase.

Ordinarily, more than 1100 product units and over 1.8 million unit hours of burn? in data have shown no failure at all that can be attributed to the ONO antifuses. This is in agreement with the prediction based on wafer level tests and the 1/E model.

References

[1]

A.

Haines, "Field-Programmable Gate Array with Non-Volatile Configuration,"

Microprocessors and Microsystems, Vol.

13, No.

5, pp. 305-312, June, 1989.

[2]

A.

El Camal, J.

Greene, J.

Reyneri, E.

Rogoyski, K. El-ayat, and A.

Mohsen, "An Architecture for Electrically configurable Arrays,"

IEEE J.

Solid-State Circuits.

Vol 24, No.

2 pp. 394?398, Apr.

1989.

[3] Preliminary data from a military system manufacturer. Test done on total dose Gamma Irradiation Survivabifity Test.

[4]

E.

Hamdy, J.

McCollum, S.

Chen, S.

Chiang, S.

ELtoukhy, J.

Chang, S. Speers, A.

Mohsen, "Dielectric Based Antifuses for Logic and Memory ICs,"

IEDM Tech.

Digest, pp. 786?789, 1988.

[5]

K.

Boyho, D. Gerlach, "Time Dependent Dielectric Breakdown of 210 A Oxides," Proc.

Int. Rel.

Phys. Synp. pp.

1-8, 1989.

[6]

I.

Chen, S.

Nolland, C.

Hu, "Electric Breakdown in Thin Gate and Tunneling Oxides,"

IEEE Trans.

Electron

Devices, ED-32, No.

2, pp. 413?422, Feb.

1985.

[7]

S.

Sxe, "Physics of Semiconductor Devices",

2nd Edition, John Wiley and Sons, Inc. pp 402-407, 1981.

[8]

A.

Nishimura, S.

Murata, S.

Kuroda, 0.

Enomoto H. Kitagawa, and S.

Nasegawa, "Long Term Reliability of Si02/SiN/Si02 Thin Layer Insulator Formed in 9 um Deep Trench on High Boron Concentrated Silicon," Proc. Int. Rel.

Phys. Symp.

pp. 158?162, 1989.

[9]

Y.

Ohji, T.

Kusaka, I.

Yoshida, A.

Hiraiwa, K.

Yagi, and K.

Mukai, and 0. Kasa-

hara, "Reliability of Nano-Meter Thick Multi-Layer Dielectric Films on Poly-Crys-talline Silicon,"

Proc.

Int.

Rel.

Phys.

Symp. pp. 55-59, 1987.

[10] P. Hiergeist, A. Spitzer, and S.

Rohl, "Lifetime of Thin Oxide-Nitride-Oxide Dielectrics within Trench Capacitors for DRAM's,"

Trans. Electron devices, Vol.

36, No.

5, pp. 913?919, May, 1989.

[11] D. Walters. J. van der School, "Dielec-tric Breakdown in MOS Devices, Part I, II, III,"

Phillips J.

Res.

Vol.

40, pp.

115?192, 1985.

[12] D.S. Peck and O.D.

Trapp, "Accelerated Testing Handbook," pp. 5-36 to 5-37, 1987.

Quality & Reliability Report 73

0ctel Table 1 Field accelerated test data for two lots with thickness ranging from 8nm to 9.5nm.

The test was done on 0.04mm2 area capacitor Lot A Lot B Voltage Tox E-filed # of cap t50 Voltage Tox E-filed # of cap t50 (V)

(n)

(MV/cm)

(sec)

(V)

(nm)

(MV/cm)

(sec) 13.5 8.3 16.2 22 4.2e-3 14.0 B.7 15.9 25 9.8e-3 12.5 8.3 15.1 22 3.7e-2 13.0 8.7 14.9 25 5.0e-2 12.0 8.3 14.4 22 1.53-1 12.5 8.7 14.3 25 2.4e-1 11.5 8.3 13.8 22 8.6e-1 12.0 8.7 13.7 25 1.3e0 11.0 8.4 13.1 22 4.7e0 11.4 8.7 13.1 25 9.OeO 10.5 8.4 12.5 9

5.8ei 11.2 8.7 12.5 45 8.Oel 10.0 8.3 12.0 6

3.2?2 10.8 9.0 12.0 45 3.52e2 9.5 8.3 11.4 6

2.5?3 10.2 9.0 11.3 45 2.88e3 9.0 8.3 10.7 36 2.5?4 9.7 9.0 10.8 45 2.07e4 8.5 8.3 10.2 15 2.3e5 9.0 8.7 10.3 32 3.35e5 8.0 8.3 9.6 59 1.5e6 9.0 9.3 9.7 32 2.22e6 Sub-total of tested cap.

241 401 Total of tested cap.

642 Table 2 High temperature operating life test data (HOTL).

Device

of

of fuse per Device Hours @

fuse Equivalent Device Units unit 125*C/5.5V*

Fail House @ 55 0 C PROM64 275 65,536 450,000 0

18.8 Million 1003JLCC 238 40,000 359,400 0

15.0 1OOJLCC 144 112,000 283,000 0

11.8 1020JLCC 61 186,000 90,000 0

3.8 1OOPLCC 358 112,000 616,000 0

25.B 1o20PLCC 32 186,000 5,300 0

0.2 Total 1108 701,536 1,804,100 0

75.5 Million I L IL ILI L D

b me IQ__

L4 E

wo *luI~

II I

mmelL

-7A r-

~1~WTW "PM.

"PI woos Fig.

1 ONO antifuse has a tighter resistance distribution than oxide antifuse.

Fig. 2 Simplified product architecture show-ing logic modules, routing tracks, and anti-fuse arrays.

Vpp is applied to program a

selected antifuse. Unselected antifuses have Vpp/2 or 0V stress.

74 Quality & Reliability Report

Mctef 1.01.0?'VI 1.06.a As A

0 0

i.0E-1.07 X

1.01E.02 4

1.1101 0

1.06.0 N.*

+

1.06-041

.i

~

4N**e*

+

1.

+,

1.0E-02 1.01E-e l.0l I04 p C

I i

8:

I0 1"E s

.o:,

30 go~qog ogoeo go go.u g

age

CumulatWn F&nm (%)

Fig. 3 Cumulative percentage failure versus time on a log-normal scale.

10o/E (cMfMV)

W 11 a

Fig.

5 Log t 50 vs l/E for two area capacitor was used.

lots. O.o4mm2 iNw*WNM GRAPHICS PLOT ******

S0.04,M POWLIN-N*o

oE*

TDDB (ees) 1.01.0l1

.E.07

+ LOG A 0LOO 1.01E.01 1.0E-04 1.-014 1.01[-03

-s

4 1.06-00 1.3-01 s

1.o1-02 1.1E-03 a

10 11 10 U

a 14 I

1 17 E (MV/cm)

Fig.

6 Log t 5 0 vs E for two lots.

Log t1 0 haE a similar E dependence.

Correlatkou CoefliclentlR oqawo) 0.9c 0.908.

0.960 0.984 0.9882 0.98 0.978 6

N*N** GRAPHICS PLOT How*I 0.040W,-6 19OOIL

%E+01 decode

/01V FF1

I

.T_

.1.-

p.

f:~ ~F

-2

-1.6

-1 0

0.

n(exponent of E field dependence)

I 1.6 4.000

1109W, 1.000/0iv

+4.00 E.00 Fig. 4 I-V characteristics of

oxide, nitride, and ONO.

(a)

Fouler-Nordheim tun-neling plot.

(b) J vs E plot. Log(J) of ONO is not a linear function of l/E I-V.

Fig. 7 t. 0 was fitted to 5 different distri-bution. The fitting correlation coefficient (R 2) is plotted against the field exponent n in

[exp(En)].

i/E(n=-l) has the best fit with the largest correlation coefficient.

Quality & Reliability Report 75

__0Ct0I Activation Enerm, (eV) 0.4-0.2-0.1.

00 U

U012 1

14 15 E-FMeW (MV/cra) 16 16 17 7

a 100/! (cm/MV) 10 11 1

Fig.

8 Residuals at each data point are plotted for 5 different n's. E field depen-dence has the largest residuals.

l/E and l/DE have the smallest residuals.

TODD (seod t.0EoiC I.09 40 AM E010.

8hle Fko. 3JuMd 1.11.00 Capection n3 t16.0 IM p rsduci 0.3OUI2 1.A1.01 100/! (cm/MV)

Fig.

9 Log t 5 0 can be fit as a linear func-tion of l/E with the same slope for three different structures: single fuse (3.2um2 ),

area capacitor (0.04mm2 ),

and product array (0.35mm2 ).

TDDB (eec)

Fig.

11 energy.

Field dependence of ONO activation IA0E-04 1.4DE.54 1.51.02 1.56.00 10E-01 Cumunaive MeUrM (M)

Fig. 12.

Cumulative percentage failure of product antifuse array (0.35mm 2) vs break-down time at 11V stress.

i 1.OE0110 1.01051 1.01.04 1.06.03 1.01E.02 1.E-10 1.51-00 1.01-01 MVIM

10-I IA 114.3-Wafer No..

I Fiq.

13 A typical wafer sort yield loss plot

!M.IS-2 La a

1000/T (1/KeCvin Fig.

10 Field affect on t 50 at temperatures ranging from 25 0 C to U

A for one lot. After the screen, the 10 run average yield lose is less than 0.3%.

Since the screen is more severe than 5.5V/40 different

years, the product will be very reliable 150oc.

throughout the operating lifetime.

76 Quality & Reliability Report

~CteI Antifuse

+

Diffusion R

Poly Fig.

14 A four terminal Kelvin structure is used for programmed antifuse reliability test.

When an open failure is detected through two stressed terminals, A and B, the antifuse resistance remains low as measured through two unstressed terminals, C and D.

Fig. 16 SEM photograph of the Kelven struc-ture after showing an open circuit. The open is identified to be at poly to metal contact due to contact electromigration.

of W

12 S25(fC, SmA Test A

7 2

1 226IOldM8323@3*344 ELAPSED TIME (HOURS)

Fig. 15 Voltage across antifuse versus stress

time, with 5mA current.

Antifuse resistances remains little changed prior to contact failure.

Quality & Reliability Report 77

Sctel C. Reliability of Actel Metal-to-Metal Antifuses Introduction Metal-to-metal antifuses are attractive for use as programmable interconnect elements for high-performance, high-density Field-Programmable Gate Arrays. Relative to other programmable interconnect elements such as SRAM or EEPROM cells or even ONO-antifuse cells, metal-to-metal antifuses have smaller size, lower capacitance, and lower programmed resistance, making them ideal for this application.

Metal-to-metal antifuses do have their own set of design, processing, screening, and testing requirements. At Actel these requirements have been extensively studied. An optimal solution for the antifuse materials and structure, as well as process monitoring, screening, and product reliability testing has been created that ensures a high-performance and reliable product.

Antif use Structure and Characteristics Figure C-I is a schematic representation of the Actel metal-to-metal antifuse structure. This structure has been implemented in three-layer metal 0.6um and 0.35um CMOS processes; metal 2 is the bottom electrode and metal 3 is the top electrode. The antifuse structure and materials are optimized to meet requirements of low capacitance, low leakage, low programmed resistance, and high off-state (unprogrammed) and on-state (programmed) reliability.

Proprietary metal layers abut the dielectric and amorphous silicon which form the antifuse.

Metal-3 Top Electrode Amorophous Silicon Dielectric Bottom Electrode Metal-2 Figure C-1 Antifuse Cross-Sectional View 78 Quality & Reliability Report

Unprogrammed Antifuses Table C-I compares capacitance of Actel antifuses from the 0.6um process generation through the 0.25um process generation. These are the total capacitances per antifuse cell pitch, including metal line capacitance, and, in the case of the ONO antifuse, other parasites such as n+ diffusion capacitance.

Table C-1 Typical Unprogrammed Antifuse Capacitance Including Metal Fringing, Per Cell Process Capacitance 0.6um ONO:

7.7 fF 0.6um M/M:

2.9 fF 0.35um M/M:

1.6 fW 0.25um M/M:

0.8 fF Leakage in unprogrammed amorphous silicon-based antifuses varies exponentially with voltage, as well as with temperature. Thus the equivalent resistance is a function of both. The antifuse is designed so that its leakage characteristics are consistent with data sheet standby Idd limits over voltage, temperature, and operating lifetime. This is discussed in more detail below.

Programmed Antifuses Programming is accomplished by applying a series of high-voltage pulses across the selected antifuse. A metal silicide link isformed through the dielectric and amorphous silicon, resulting in a low-resistance path.

The breakdown voltage distribution for single antifuses is shown in Figure C-2. Distributions are tight, which is critical for the programming and reliability of the antifuses. Ramp rate was

0. 1 V/imS; temperature 25°C.

Quality & Reliability Report 79

-Mctel 0.999 0.99 i0.9

V+

on top electrode 0.8 0.6 0.4

~0.3 0.2 0.1 V-on top electrode 0.01 I

I I

0.001 8

8.5 9

9.5 10 10.5 11 Breakdown Voltage (V)

Figure C-2 Breakdown Voltage Distributions Table C-2 compares resistance of Actel antifusesfronm the 0.6um process generation through the 0.25um process generation. A programming current of 20 mA was used for this particular comparison. Programmed metal-to-metal antifuse resistance is about a factor of 5 lower than that of the ONO antifuse, at a given programming current.

Table C-2 Typical Programmed Antifuse Resistance at Ipp = 20 mA Process Resistance 0.6um ONO:

125 ohms 0.6um M/M:

25 ohms 0.35um M/M:

25 ohms 0.25um M/M:

25 ohms Figure C-3 shows programmed antifuse resistance distributions for different programming currents. Figure C-4 shows average programmed antifuse resistance as a function of programming current. The resistance of programmed antifuses is stable with temperature, varying less than 15 percent per 100°C.

80 Quality & Reliability Report

_404tel A

1,,

0.999 Ipp= 25 mA

,20 m 15 mA 10 m A 01.8 10.9 0

EI 0.6 0.5 0.4 E

0.3 E.10.2 0.1 II 0.01 2\\'

1 I

I I

0.001 0

10 20 30 40 50 60 70 80 On-state Resistance (Ohms)

Figure C-3 Programmed Antifuse Resistance Distributions

Z 100 E

0 80 C1 C2 Ron=

+

2.

" 60

/Pp T)

4) 40 20 0

0 0

5 10 15 20 25 30 Ipp (mA)

Figure C-4 Antifuse Resistance vs. Programming Current Quality & Reliability Report 81

_ Octel Reliability Characterization and Modeling Unprogrammed Antifuses Two possible failure modes Jfr unprogrammed amorphous silicon-based antifuses can be considered:

I Increase in leakage over time, leading to high standby ldd 2

Breakdown (unintentional programming), leading to functional failure Both of these failure modes have been characterized in highly accelerated testing of single antifuses and antifuse arrays. Failure is accelerated by applying high voltage and/or high temperature to the test structures. Figure C-5 shows time-to-breakdown distributions at various stress voltages.

0.99 0.95 Vstress =8.5V 8.0V I

7.5V 7.0V 0.9 0.8

/M 0.7 0

.0.6 C

1 '

0.5 I) 0.4 0.3 cc 0.2 E

0.1 0

0.05 0.05 I

I I

0.01 1E + 00 1E + 01 1E + 02 1E + 03 1E + 04 1E + 05 1E + 06 Time (sec)

Figure C-5 Time-to-Breakdown Distributions We have found that for outr dielectric/amorphous silicon antifuse, leakage current increase at normal stress voltages is not a concern for our product. In order to demonstrate this, we have examined the use of ] and 10 nA per antifuse at 3.6 Vas the failure criterion, as well as a failure criterion for dielectric-like breakdown of 1.0 mA at 3.6V.

Additionally, we have found that a I/E model is an adequate and conservative way to model time to failure over the range of interest (between 0. 1 second and 20 years).

82 Quality & Reliability Report

Ofctel Figure C-6 and Figure C-7 show the median time-to-fail versus I/V for single antifuses with positive voltage stress on the top electrode and ambient temperatures of 25'C and 150'C, "respectively.

Figure C-6 Time to Breakdown vs. 1/V, 250C 1E+10

/

1 E + 09

-Single antifuse Stress polarity: Positive top electrode 1E+08 Ta=25-C 1"

1E+07 1E+06 L

1E+05 1 E+04 N

1 mA criterion (breakdown) 1 E + 03 A

1

/

1 A criterion 1 E + 02 A

1 nA criterion 1 E + 01 1 E +00 0.1 0.15 0.2 0.25 0.3 1N(*N)

Figure C-7 Time to Breakdown vs. 1/V, 1500C Quality & Reliability Report 83

Mctel Figure C-8 shows the median time-to-failfor single antifuses and 1000-antifuse arrays with positive voltage stress on the top electrode at an ambient temperature of 150 'C. Failure criterion is breakdown.

1E+10 Stress polarity: Positive on top electrode E+0 Ta = 1501C S

1 E + 08 1 mA criterion (breakdown)

=

1E+07 6

1E+06 1E-+-05 E

1E+04 -

1" 1E+03

-li ARU Single antifuse 1E+02

-1 S[

1 K array 1E+01 1E+00 1 1

0.1 0.15 0.2 0.25 0.3 1IN (1N)

Figure C-8 Time-to-Breakdown vs. 1/N, Single Antifuses and 1000-antif use Arrays The results in Figure C-9 show the dependence of off-state lifetime as a function of ambient temperature. Activation energy for off-state lifetime can be determined using an Arrhenius model for the temperature dependence. The value of the activation energy is approximately 0.3 eV 1E+06 Stress Voltage 7.5V 1E+05 cc 1E+04 a) 1E+03 1E+02 1E0 2

1E+01 1E+ 00 1

1.5 2

2.5 3

3.5 4

4.5 5

1 000/T (11/K)

Figure C-9 Time-to-Breakdown vs. 1/T 84 Quality & Reliability Report

_ ctel Thus a conservative model for failure of unprogrammedActel antifuses is t50 = A *exp(-G*V,)exp(Ea/kT) where G depends on film thickness Ea - 0.3 Programmed Antifuses Programmed amorphous silicon-based metal-to-metal antifuses can be caused to fail by applying a high AC read current. The failure mechanism is similar to metal line electromigration, although here the current acceleration is much more significant than ambient temperature acceleration. Figure C-J0 shows programmed antifuse time-to-failure distributions at several different stress currents. The stress used is a 1 MHz AC signal at an ambient temperature of 25°C.

0.99 Programming Current = 25 mA Istress 18.5 mA f,-0.95 0.9 W

-0.8 18.0 mA 0.7 0.

("

1<':

0.6 G) 0.5 2

ILI 17.0 mA 0.4 cc 0.3

/'

0.2 E"I' 0

0.1 1

0.05 I

I I

I0.01 1E+00 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 Time (sec)

Figure C-10 Time-to-failure Distributions Figure C-l shows programmed antifuse (on-state) lifetime as a function of programming current and stress current. The median time-to-fazil datapoints above IE7 seconds are extrapolated using the observed log-normal sigma.

Quality & Reliability Report 85

~cte~

1 E + 12 Experiment:

9 A Model:

S1E+1O 1 MHz, AC stress lO j

1E+08 e o d

1E+04 C

EE

1E+0 24 p

=1 mA 2 m U)o U

1E+10 1

Ipp~m' l~m i~mA25 m

0 5

10 15 20 25 30 Peak stress current (mA)

Figure C-ll Time-to-Failure vs. Stress Current

(

The model used for on-state lifetime is t5O = Aexp(Ea/kTmax) where Ea - 2 eV Tmax is not the ambient temperature, but rather the maximum temperature in the antifuse link.

Tmax = Ta + 12

Rfuse

Theta I is the stress current Rfuse is the antifuse resistance (also temperature-dependent)

Theta is the thermal resistance of the link.

We have seen that time to failure in programmed antifuses is only weakly dependent on ambient temperature, but strongly dependent on stress current, as expected. Figure C-12 shows median-time-to fail vs. peak stress current for two different temperatures: 25'C and 125°C.

Frequency, waveform, and duty cycle of the stress pulses can also have some effect.

86 Quality & Reliability Report

~cteI 1E + 12 Experiment:

A Eyring Model: -

O 1E+10 1 MHz, AC stress Ipp 25 mA 1E+08 E

1 E + 06 1 E + 04 Ta =125°C 25°C 2

1E+02 1 E + 00

__j 0

5 10 15 20 25 Figure C-12 Time-to-Failure vs. Stress Current For Different Ambient Temperatures Designing for Reliability Unprogrammed Antifuses During normal operation, voltage across unprogrammed antifuses is limited to VCCA, the array VCC. For example this is a maximum continuous voltage of 3.6V for 0.35um process parts, and 2.8Vfor 0.25um process parts. I/Os may operate at higher voltages but the antifuses are isolated from them.

A relatively high ratio of programming voltage to operating voltage (Vp/IVCCA) is used to ensure that leakage conforms to data sheet standby Idd limits over a 20-year lifetime, and so that low breakdown antifuses can be screened out during final test using a special screen.

Programmed Antifuses The design of the programming path ensures that the programming current is sufficient to create a robust antifuse link.

The programming algorithm, a function of both the product circuitry and the programming hardware, is optimized to minimize programming time, minimize programmed antifuse resistance, and maximize reliability.

From statistical analysis of data on time-to-failure of programmed antifuses, a safe operating area for stress current at a given programming current has been defined. The product operates within this area for the worst-case process, programming path, and the worst conceivable customer designs.

Quality & Reliability Report 87

Ofctel Process Monitoring for Reliability Unprogrammed Antifuses During electrical test (e-test)for wafer and lot acceptance, several antifuse parameters are datalogged in addition to the standard CMOS process parameters. These include:

Breakdown voltages for single antifuses and arrays, for both polarities N Antifuse array leakage at several voltages, for both polarities

Antifuse array capacitance Leakage after a high-voltage, I second screen on a large antifuse array, for both polarities.

These tests can catch process problems and provide a basis for rejecting defective wafers or lots.

Programmed Antifuses The following are also monitored as part of wafer/lot acceptance:

Programmed antifuse resistance Threshold voltages and saturation current for high-voltage (programming) transistors.

Product Screening for Reliability Unprogrammed Antifuses During wafer sort and final test operations, all antifuses on every product are subjected to high-voltage screens, designed to weed out parts which could fail during normal operation over the life of the part. Each of these "antifuse stress" screens is on the order of twice the normal VCC, for a duration of about 0. 1 seconds.

The data from the pair of screens is used in two ways: First, if an antifuse fails during the screen (detected by leakage in a special test mode), the die or assembled part will be rejected. Second, data from both screens is used to give some resolution of the shape of the unprogrammed antifuse breakdown distribution, and criteria are in place that provide a basis for rejecting wafers or lots based on the results of these screens.

Programmed Antifuses Since antifuse-based FPGAs are one-time programmable, any reliability screen done for programmed antifuses must'be done at the time of programming.

We have found that there is a high correlation between initial programmed antifuse resistance and subsequent on-state reliability. Thus if the resistance of an antifuse is too high after programming, the part will be rejected as a programming failure.

88 Quality & Reliability Report

Sctel In practice an indication of the antifuse resistance is obtained during product programming, by monitoring current through each antifuse at reduced voltages, after it is programmed. This is done automatically by the programming hardware and software. If an antifuse can not be programmed to a suitably low resistance, the part will be rejected as a programming failure.

Other infant mortality failure mechanisms such as gate oxide breakdown or open vias may also cause the part to be rejected as a programming failure.

Product Testing for Reliability Product-level testing for reliability includes process/product qualification testing, ongoing reliability testing, and QA monitors. In addition, more severe engineering characterization of products has been done and is ongoing.

Unprogrammed Antifuses The standard qualification test that is most indicative of unprogrammed antifuse reliability is the High-Temperature Operating Life (HTOL) test. For 3.3V (VccA) SX products, the test condition is VCCA

= 4.0 V Ta

=

125 0C Duration =

1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months Based on our model for voltage and temperature acceleration offailure of worst-case unprogrammed antifuses, this test condition provides an acceleration factor in excess of 200x relative to an operating condition of VCCA = 3.6V, Tj = JOOC.

The HTOL test is also an effective way to accelerate other failure mechanisms such as gate oxide breakdown, metal line electromigration, mobile ionic contamination degradation.

In addition to the initial qual testing, Actel's Ongoing Reliability Testing (O.R.T) program provides fbr continuing HTOL testing on a sample basis.

Programmed Antifuses Failure in Actel programmed metal-to-metal antifuses is strongly dependent on the stress current going through the programmed antifuses, and only weakly dependent on the ambient temperature. Thus the best way to accelerate failure in programmed antifuses is to do a high-Vcc, low-temperature dynamic burn-in. Both the high VCC and low temperature increase the peak stress current going through the antifuse. Our qualification test condition for this Low-Temperature Operating Life (LTOL) Test is VCCA

= 4.0 V Ta

-55 0C Duration

1000 hours0.0116 days 0.278 hours 0.00165 weeks 3.805e-4 months Quality & Reliability Report 89

_ 7 ctel Based on our model for current acceleration offailure of worst-case programmed antifuses, this test condition provides an acceleration factor in excess of 200x relative to an operating condition of VccA = 3.6V, Tj = O°C.

In addition to the functional testing done at each time point, the special burn-in designs used in this test allow us to catch transient failures that might occur in between the functional testing time points. Parts under test are continuously monitored for transient failure of programmed antifuses.

The LTOL test is also an effective way to accelerate degradation and failure associated with hot-carrier effects.

As with the HTOL test, sample LTOL testing is done as part of Actel's Ongoing Reliability Testing (O.R.T) program.

Conclusion Assuring reliability ofActel Metal-to-Metal antifuse-based Field-Programmable Gate Arrays is a multifaceted task that starts with process design and product architecture. It involves special wafer and lot acceptance criteria, as well as product-level screens designed to identify and discard any products that would fail during normal operating conditions. Qual test conditions and burn-in designs are optimized to catch antifuse-related failures in addition to the standard CMOS process failure modes. Quality is assured by ongoing reliability testing.

Product reliability data can be found in SX product family reliability reports.

References

[1]

C. Shih, R. Lambertson, F Hawley, F Issaq, J. McCollum, E. Hamdy, H. Sakurai, H.

Yuasa, H. Honda, T Yamaoka, T Wada, C. Hu, "Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and High-Density Field-Programmable Gate Arrays" in Proceedings of 1997 Reliability Physics Symposium, pp. 25-33, 1997.

[2]

S. Chiang, R. Foruohi, W. Chen, F. Hawley, J. McCollum, E. Hamady, and C. Hu, "Antifuse Structure Comparison for Field Programmable Gate Arrays," IEEE IEDM Tech. Dig., pp. 611-614, 1992.

[3]

C. Hu, "Interconnect Devices for Field Programmable Gate Array," IEEE IEDM Tech.

Dig., pp. 591-594, 1992.

[4]

S. Cohen, A. Soares, E. Gleason, P. Wyatt, and J. Raffel, "A Novel Metal-Insulator-Metal Structure for Field-Programmable Devices," IEEE Trans. Electron Devices, Vol. 40, pp.

1277-1283, 1993.

[5] K. Gordon and R. Wong, "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse, " IEEE IEDM Tech. Dig., pp. 27-30, 1993.

90 Quality & Reliability Report

_:actel

[6] M. Takagi, I. Yoshii, N. Ikeda, H. Yasuda, and K. Hama, "A Highly Reliable Metal-to-Metal Antifuse for High-Speed Field Programmable Gate Arrays," IEEE IEDM Tech. Dig., pp. 31-34, 1993.

[7]

K. Ravindhran, L. Vines, R. Jhota, T Han, and B. Bhushan, "Field Programmable Gate Array (FPGA) Process Design for Multilevel Metallization Technology," in Proceedings of 1993 VMIC Conference, pp. 62-64.

[8]

Y Tamura and H. Shinriki, "Most Promising Metal-to-Metal Antifuse based lOnm-thick p-SiNx film.for High Density and High Speed FPGA Application," IEEE IEDM Tech.

Dig., pp. 285-288, 1994.

[9]

R. Wong and K. Gordon, "Reliability Mechanism of the Unprogrammed Amorphous Silicon Antifuse," in Proceedings of 1994 Reliability Physics Symposium, pp. 378-382, 1994.

[10] P Nicollian and W. Hunter, "Modelfor the Leakage Instability in Unprogrammed Amorphous Silicon Antifuse Devices," in Proceedings of IEEE Reliability Physics Symposium, pp. 42-47, 1995.

[11] H. Yasuda, N. Ideda, K. Hama, M. Takagi, and L Yoshii, "Relation Between Stress-Induced Leakage Current and Dielectric Breakdown in SiN-based Antifuses," in Proceedings of IEEE Reliability Physics Symposium, pp. 225-23 1, 1994.

[12] G. Zhang, C. Hu, P. Yu, S. Chiang, S. Eltoukhy, and E. Hamdy, "Reliable Metal-to-Metal Oxide Antifuses," IEEE IEDM Tech. Dig., pp. 281-284, 1994.

[13] Y Tamura and H. Shinriki, "ON-state, Programming and OFF-state Reliability of Metal-to-Metal Antifuse based 10 nm-thick SiNx film for 3.3 V Operation," in Proceedings of IEEE Reliability Physics Symposium, pp. 36-41, 1995.

[14] US Patent number: 5,181,096.

[15] G. Zhang, C. Hu, Y Yu, S. Chiang, S. Eltoukhy, and E. Hamdy, "An Electro-Thermal Model for Metal-Oxide-Metal Antifuses," IEEE Trans. Electron Devices, vol. 42, pp.

1548-1558, 1995.

[16] G. Zhang, C. Hu, P. Yu, S. Chiang, and E. Hamdy, "Characteristic voltage of the programmed metal-to-metal antifuses," IEEE Electron Device Lett., vol. 13, pp. 166-168, 1994.

[17] D. Crook, "Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown," in Proceedings of IEEE Reliability Physics Symposium, pp. 1-7, 1979.

[18] E. Anolick and G. Nelson, "Low Field Time Dependent Dielectric Breakdown," in Proceedings of IEEE Reliability Physics Symposium, pp. 8-12, 1979.

[19] 1. Chen, S. Holland, and C. Hu, "A Quantitative Physical Model for Time-Dependent Breakdown in Si02, " in Proceedings of IEEE Reliability Physics Symposium, pp. 24-31, 1985.

[20] G. Zhang, Y King, S. Eltoukhy, E. Hamdy, T Jing, P. Yu, and C. Hu, "On-state Reliability of Amorphous Silicon Antifuses," IEEE IEDM Tech. Dig., pp. 551-554, 1995.

Quality & Reliability Report 91

Actel and the Actel logo are registered trademarks of Actel Corporation.

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http://www.actel.com Actel Europe Ltd.

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