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Emergency Response Facilities Info Sys Isolator Type Test Summary
	ML20196E276
Person / Time
Site:	Vermont Yankee File:NorthStar Vermont Yankee icon.png
Issue date:	12/05/1988
From:	; VERMONT YANKEE NUCLEAR POWER CORP.
To:	;
Shared Package
ML20196E273	List: FVY-88-100, Forwards SPDS Isolator Test Results; ML20196E276;
References
	NUDOCS 8812090307
	Download: ML20196E276 (41)
	v • d • e

{{#Wiki_filter:_ . - s 7 VERMONT YANKEE NUCLEAR POWER STATION Emergency Response Facilities Information System Isolator Type Test Summary i l l l 1 t Attach,wnt to Ve:mont Yankee letter FVY 88-100, dated 5 December 198S GG12090307 681205 PDR ADOCK 05000271 P__ ______ _ F D C _ _ _ . _ _ __ . ___ _ _ _ _ ._ .__

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ISOLATOR TYPE TEST I. EQUIPMENT Type testing on prototype units was performed to prove the design adequacy of tne following equipment: Dese,ription Patt Number Secondary Part Number Single-Channel Analog BVY-E028DD-1 SCA 100-10-10-02 Isolator Single-Channel Analog BVY-E029DD-1 SCA 100-05-06-02 Isolator Four-Channel Analog BVY-E018DD-1 FCA 300-02-06-02 Isolator Four-Channel Analog BVY-E019DD-1 FCA 300-04-06-02 Isolator Four-Channel Analog BVt-E020DD-1 FCA 300-03-06-02 Isolator Four-Channel Analog BVY-E021DD-1 FCA 300-05-06-02 Isolator Fnur-Channel Analog BVY-E022DD-1 FCA 300-07-06-02 Isolator Single-Channel Digital SCD-E200DD-1 SCD 200-01-02 Isolator 4 Single-Channel Digital SCD-E201DD-1 SCD 200-02-02 Isolator Tour-Channel Digital FCD-E400DD-1 FCD 400-01-02 Isolator Four-Channel Digital FCD-E401DD-1 FCD 400-02-02 Isolator II. TEST CONDITIONS In additioa to the normal factory tests prototype isolators chosen from the regular production run were subjected to type qualification tosts. These tests were designed to verify that the isolators are capable of performing the isolation function specified in (EEE Standard 334-1981. All testing, excspt thermal stability testing, was condected on unpotted , units. This was done in order to allow a detailed examination of the 7051R

. s l ' post-test isolators to determine the extent, if any, of damage. Testing i of unpotted units is conservative since the potting material will provide additional insulation between the various conductors within the isolator. In general, identical tests were performed on both single-channel and

>                    four-channel isolators. However, some destructive tests were only

performed on only one model. Specifically, the following tests were performed only on the isolators indicated

i~ Test Isolators Utilized 140 V de Output Fault Four-Channel Analog i Four-Channel Digital i l Power Supply 480 V ac Fault Single Channel Analog j The critical components utilized are identical between the single-channel and the four-channel isolator of each type; therefore, isolator response to the 140 V de test would be similar. This is further corroborated by

the more severe 480 V ac output fault test which was conducted on each type.

The internal power supply is identical in all isolator designs. Therefore, the successful test, utilizing the more severe 480 V ac fault, of the single-channel analog isolator provides sufficient verification of the adequacy of the design of all four isolator types. III. PERFORMANCE SPECIFICATIONS The isole. tors being utilized at Vermont tankee have been proven to meet, or exceed, the following specifications: A. GENERAL ISOLATOR SPECIFICATIONS

1. Dielectric Withstand:

Input to Outputt 3,000 V de 9 < 10 uA de 1,500 V ac 9 < 1 mA ac Input to Caaer 1,000 V de 9 < 10 uA de 1,000 V ac 9 < 1 mA ac

2. Output Fault Withstand (Effect of an Output Fault on the Input Signal):

Shorts. Opens, Grounds: No Effect 480 V ac or 140 V de 9 20 amps: < Input Full Scale and Lasting < 40 msec

3. Surge Withstend Capability: Per IEEE 472-1974 on Input, Output, and Power Te rminals

4. Seismic (by Analysis): Per IEEE 344-1915 7051R m

s B. ANALOG ISOLATOR SPECIFICATIONS

1. Accuracy: 10.1% of Output Full Scale

2. Linearity: Better Than 0.1% Output Full Scale

3. Temperature Stability: 1005% of Output Full Scale / Degree C

4. Frequency Response de to 5k Hz C. DIGITAL ISOLATOR SPECIFICATIONS

1. Response Times de Input Models: <0.4 msec (by Calculation) ac Input Models (30 msec (by Calculation)

IV. TEST

SUMMARY

- ANALOG ISOIATORS A. Functional Test and Linearity (Figure 1-1)

1. Test Description - Inputs of 0%, 50%, and 100% of the rated input span were applied and the output signal measured. Both the input and output signals were measured with calibrated digital multimeters to verify that the isolator functioned in accordance with the design specifications. Additional adjustment capability was also verified for the offset and gain at this time. For linearity, input signals of 0%, 20%, 40%,

60%, 80%, and 100% of input full scale were applied to the isolator input terminals. The test was repeated twice, once with signals going from 0% to 100% and once with signals going from 100% to 0%.

2. Results - The output signal response measured for all the inputs was within the design tolerance of 10 1% of the output span. The isolator had more than 15% of the adjustment still available in the offset and gain potentiometers. Linearity was determined to be within 0.1% of the output span for all points taken.

B. Hi-Potential (Isolation Tests) (Figurr4 1-2A through 1-2C)

1. Test Description - Input to out put hi-potential testing was performed by applying 3,000 V .c from all of the input to all of the output terminals of the isolator. The test was then repeated vs.'e 1,500 V ac across the same points. Power supply to input hi-posantial testing was from the power supply inputs to all the signal inputs simultaneously and used voltages of 1,000 V de and 1,100 V ac. Input to ground hi-potential 7051R

k testing was performed by applying the same voltages from all input terminals simultaneously to ground (case). Power and input signals are not connected during this test.

2. Results - During application of the de voltages, the leakage current is so small as to be unmeasurable. The high voltage was applied for approximately five seconds with no increase in the current, thereby ensuring no breakdown of isolation. The ac high voltage was applied for approximately 60 seconds with no increase shown in the leakage current. Testing experience has shown that the extremely small amount of leakage current detected is f rom capacitive coupling of internal wiring and leads inherent in any test of this nature.

C. Surge, Withstand (Figures 2-1A through 2-1F)

1. Test Description - Surge withstand capability testing of the isolator was performed by applying an IEEE 472 surge waveform to the isolator in six configurations comprising the possible common and transverse modes for a surge to occur: input transverse, input common (to ground), output transverse, output common (to ground), power supply transverse, and power supply common (to ground). For surges applied to the output and to the power supply terminals, tne inputs were monitored. Ft. r input surges, the output terminals were monitored. A functional check was run on all channals after the applica. ion of the surges to verify operation.

2. Results - Functional testing after the application of the surges showed the unit to be functional and calibration remained within the required design specifications.

D. External Ef fects Testing ( Figures 2-2A and 2-2B)

1. Power Supply Drift Test Description - The input power supply was set first to +5% and then to -51 of its nominal value with a 50% of input span signal applied to the inputs. The outputs were monitored for changes.

2. Power Supply Drift Results - The outputs all remained well within 101% of their initial values throughout the power supply voltage variations.

3. Thermal Drift Test Procedure - This testing was done on a potted isolator to more accurately represent actual service conditions. The output was monitored with a 50% of input fuit scale signal cppliod. The temperature of the operating unit was established at 5, 10, 20, 30, 40, and 50'C and data points taken.

7051R i

s 4 Thermal Drift Test Results'- The output of the isolator varied less than 0.05% of the output full scale for a temperature , variation from 5'C to 50'C. J E. Fault Testina (Figures 2-3A throuah 2-3F) , e

1. Test Description - Fault testing consisted of three I

nendestructive and three destructive tests. Fuses were bypassed, power was connected, and a 50% of input full scale signal was applied to all inputs for all testing. The . nondestructive tests consisted of opening the connections to I the output, shorting the output transversely, and shorting the t

output to ground. Two of the destructive tests consisted of !

applying 140 V de and 480 V ac across the outputs of the { isolator. The third consisted of applying 480 V ac across the- j power supply input terminals. The fault voltages were applied i with drive in excess of 10 amps. For all tests, the effects apparent at the input could not exceed the nominal input span during the fault and the input had to return within 0.1% of the prefault values within a short span of time. The isolator must 1 i pass a post-fault hi-potential test. : r (

2. Results - After the nondestructive tests, the input signal l returned to within 0.1% of the prefault values. There was no }

measurable effect on the input for the open and short circuit

tests and all outputs returned to their prefault values after i removal of the fault. When 140 V de was applied as a fault, l there was no measurable effect on the input, and all but the !

l faulted channel remained functional and returned to within 1% I of prefault values following removal of the fault voltage. The [ ! effects on the input from the 480 V ac fault were less than ! ! 0.75 V and lasted for less than five milliseconds. Due to [ ! damage to the surge components, no channel still operated r through to the terminal strips; however, on the four-channel j l i isolator, the three channels not subjected to the fault still j functioned at the output of the isolation device and were found : j to still be functional and within the limits stated above. The [ i nonfunctional items for each of the output fault tests were the j output stage of the isolation device and the aarge components ; i in the output circuits. The power supply fault caused damage l l to the line fuse holders and surge protection varistors. t

Hi-potential tests were run between each set of tests, and all [

l channels of the isolator maintained isolation at all times, j There was no measurable degradation of isolation even under the , j conditions of extreme stress induced during the destructive l testing. i l L V. TEST

SUMMARY

- DIGITAL ISOLATORS A.                                                Functional Test (Figure 3-1) l

1. Test Description - A voltage of the appropriate magnitude was l

applied to each input, and the correct power supply was 7051R j i i

e connected to the power stpply terminals. Each output was measured with a load re6istor attached.

2. Results - The output was within one volt of the applied power supply voltage.

B. Hi-Potential (Isolation Tests) (Figures 3-2A and 3-2B)

1. Test Description - Input to output hi-potential testing was performed by applying 3,000 V de from all of the input to all of the output terminals of the isolator. The test was then repeated using 1,500 V ac across the same points. Input to ground hi-potential testing was performed by applying the same voltages from the input terminals to ground (ease). Power and

 ,                        input signals are not connected during this test.

2. Results - During application of the de voltages, the leakage current was so small as to be unmeasurable. The high voltage was applied for approximately five seconds with no increase in j the current, thereby ensuring no breakdown of isolation. The ac high voltage was applied for approximately 60 seconds with no increase shown in the leakage current. The extremely small amount of leakcge current detected was from capacitive coupling of internal wiring and leads inherent in any test of this nature.

C. Surge Withstand (Figutes 4-1A through 4-1F)

1. Test Description - Surge withstand capability testing of the isolator was performed by applying an IEEE-472 surge wave form 4 to the isolator in six configurations comprising the possible common and transverse modes for a surge to occur: input transverse, input common (to ground), output transverse, output common (to ground), power supply transverse, and power supply common (to ground). For surges applied to the output and to the power supply terminals, the input was monitored. For input surges, the output terminals were monitored.

A functional and isolation check were run after the application 1 of each surge to verify operation of the isolator.

2. Results - Functional testing after the application of each of the surges showed that the unit remained functional within the required design specifications. The isolation check showed no degradation of isolation.

D. Fault Testing (Figures 4-2A through 4-2E)

1. Test Description - Fault tssting consisted of one nondestructive and four destructive tests. Fuses were bypassed, power was connected, and an input of full scale was applied for all testing. The nondestructive test consisted of 7051R

opening the connections to the output. The destructive test consisted of shorting the output transversely, shorting the output to ground, and applying 140 V de and 480 V ac across the outputs of the isolator. The fault voltages were applied with drive in excess of 10 amps. For all tests, the input had to return within 0.1% of the prefault values within a limited time span. The isolator was checked for function and isolation after each of the fault tests. When required to allow further testing, damaged components vere replaced as needed before continuing with the next test.

2. Results - The input returned to within 0.1% of the prefault values within 40 seconds of removal of the fault. There was no measurable effect on the input for the open and short circuit tests. The outputs all returned to their prefault values af ter removal of the open circuit fault. The short circuit faults both caused the optoisolator in the faulted channel to et,ase fur:tioning, but there was no measurable effect at the input.

The 140 V de fault produced no measurable disturbance on the input of the isolator. When 480 V ac was applied as a fault, there was a smal' (approximately 1 volt peak) and very short duration (less than 200 milliseconds) spike at the input. The components damaged were the output stage of the optoisolator, and during the voltage fault test, the surge components were destroyed. All of these components would be protected by the fuses under normal conditions. Hi-potential tests were run between each set of tests. The device maintained isolation at all times. There was no measurable degradation of isolation even under the conditions of extreme stress induced during the destructive testing. VI. REFERENCE DOCUMENTS A. U.S. Nuclear Regulatory Commission

1. 10CTR50.49, "Environmental Qualification of Electric Equipment Important to Safety for Nuclear Power Plants."

2. USNRC Memorandum, for Raymond F. Fraley, Executive Director.

ACRS, from Robert B. Minogue, Director, Office of Nuclear Regulatory Research. Including Enclosures (1) Revision to Regulatory Guide 1.89 and, (2) Analyses of Public Comments. B. Institute of Electrical and Electronics Engineers

1. IEEE Standard 323-1974, "Standard for Qualifying Class 1E Equipment and for Nuclear Power Generating Stations."

2. IEEE Standard 323-1983 "Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations."

7051R

3. IEEE Standard 384-1981, "Standard Criteria for Independence of Class 1E Equipment and Circuits."

4. IEEE Standard 344-1975, "IEEE Recommended Practices for Seismic Qualification of Class 1E Equipment for Nuclear Power Generating Stations."

5. IEEE Standard 472-1974, "IEEE Guide for Surge Withstand Capability (SWC) Tests."

C. Electric Power Research Institute

1. EPRI NP-3325, "correlation Between Aging and Seismic Qualification for liuclear Plant Electrical Components."

2. NSAC-58, "A Guide to Qualification of Electrical Equipment for Nuclear Power Plants."

D. Other

1. 1E Device Qualification Report, Revision 0. EI International.

2. Memorandum, H. T. Hyams to S. R. Miller, VYI 88-180, dated October 25,1988, "EI International Fault Current Analysis."

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HI POT TESTER HIGH LOW O O t a L J , L J l HI POT SETUP - CONFIGURATION *A *

FIGURE 3-2A 051 ! 13.21F IG32 A.0GN ;1 I l

                                                                                                                                                         - I.

HI--POINT CONNECTION DI AGRAM SCD /HPT-002B (HI-POT AT 3000VDC AND 1500VAC) SINGLE CHANNEL DIGITAL ISOLATORS

( h F1 russ r

==

I INPUT MODEL OUTPUT I [- r _b ~ F IN SM h- _

                         ==
                           @     t Wro nATE                           -

S @

==

_[- NC CUST NO _ POWER A { ric INPUT POWEit SOURCE OUTPUT B [ NC @_

==

SINGLE CHANNEL DIGITAL ISOLATOR cND h 3 SURCE GND F2 h h F3 L J r Hi POT TESTER H]GH LOW O O w > L J Hi POT SETUP ONFI GUR ATI ON ~B" FIGURE 3-2B 051 [43.21 FIG 323. DON:1

DMM

                                                                                                                            )
                                > 0.1J1F . > 600V rINPUT                 OUTPUT' VGLTAGE * +           "           ^

l' 'l ' SOURCE N *DMM 2 2 x

       ~
                                                                                                 =

3 3

                       > 370)1H . > 2500V 4       SCD200           4

28VDC
5 5 -

6 7

                                                       <                             , ) D7 H1 SWC                            g   r, TESTER               LOW           g i

SCOPE OUTPUT TRIG MONITOR CH-1 (lfi g CH-2 SCOPE 1 * = FLOATING OUTPUT la EXT U TRIG D7 SWC (NPUT TRANSVERSE MODE TEST CONNICTION DIAGRAM FIGURE 4-1 A . OS1 t( 43.2 ]F IG41 A. 0GN !1

y 7 DMM

                    > 0.1J1F. > 600V ^!NPUT               OUTPUT' VOLTAGE * +

ryyp db 1 1

DMM SOURCE N 2 2 x

           ,                                                                      =

3 3

             >370)lH.>2500VH                                       4 4        SCD200                                   '28VDC

5 5 x 6

8 e i D7 s I SWC H1 g ,' (, TESTER LOW g, SCOPE OUTPUT TR1G MONITOR i -- ,: , {'sg,CH-L gi CH-2 SCOPE 1 + = FLOATING OUTPUT h EXT Li TRIG D7 SWC INPUT COMMON MODE TEST CONNECTION DIAGRAM F I GURE 4 -1 B OSI :( 4 3. 2 ]F IG418. DGN ;1

t

DMM

+ -

r > 0.1)JF , > 600V 1NPUT OUTPUT, >370#H.>2500V

l' ' "

h VOLTAGE * *

                                                        "1                        +

SOURCE h DMM 2 2 x

cr ! 3 _3 4 SCD200 4 + 28VDC

5 5 -

6

                                                         *  )

e a D7 H1 SWC r, ' TESTER LOW g SCOPE CUTPUT TRIG MONITOR

                                                                    * = FLOATING OUTPUT s

I' CH-1 CH-2 SCOPE 1 I EXT U TRIG G7 SWC OUTPUT TRANSVERSE MODE TEST CONNECTION D1AGRAM F IGURE 4-1 C 0S1 : 143.23 FIG 41C.0GN;1

4 DMM r > 0.1J1F . > 600V

                .                   1NPUT         OUT3UT'_            ,,             >370J1H >2500V
                                \                                '    "

h VOLTAGE * + 1" '1 SOURCE - 2 2 FITT'- + DMM cr ! 3_ [3 K 4 4

SCD200
5 5 - 28VDC 6

7 8 e J b HI g r, SWC TESTER LOW g l . l l SCOPE OUTPUT l TRIG MONITOR

                                                                           * = FLOATING OUTPUT l

1 (l 7, CH-1 g CH-2 SCOPE l i_ i h EXT U TRIG 07 i SWC OUTPUT COMMON MODE TEST CONNECTION DIAGRAM l

l FIGURE 4-1 D OSI: ( 43. 2 )F I G410. DGN ;1

1!

O c

DMM INPUT OUTPUT'

l' 'I / DMM VOLTAGE *
SOURCE -

2 2 / - _ / 3 >, 0.1)lF . > 600V ( SCD200

                                                                        ~3 4

h

8VDC

5 5 x 7 > 37 0)1H . > 2500V

                                   .                                           ,  D7 HI SWC                                           ') (1 g

TESTER .L OV g, SCOPE OUTPUT TRIG MON] TOR

                                                                                            + = FLOATING OUTPUT CH-1 flft   CH-2 g

SCOPE 1 li EXT L' TRIG i 07 SWC POWER SUPPLY TRANSVERSEiMODE TEST CONNECTION DJAGRAM FIGURE 4-1 E 0S1 :( 43,2 JF IG41 E. DGN:1

   . ,     e I

DMM i+ ~ lNPUT OUTPUT' l* DMM

                                       ~                   ~
                                 \                               /

h . 1 1 , S00 - 2 2 ' y, _ / 3

                                                                     '0.1dF.>600V
                                                           ~3 i      SCD200           4   #

N h -'28VDC

5 5 x ,,

6

                                                                              >370)1H.>2500V 8

D7 HI - SWC LOW ! ri TESTER g SCOPE OUTPUT , TRIG MONITOR

                                                                          * = FLOATING OUTPUT I'     CH-1 fl  CH-2 SCOPE 1

h EXT U TRlG D7 SWC POWER SUPPLY COMMON MODE TEST CONNECTION D]AGRAM

F IGURE 4-1 F OS1 (43 2) FIG 41F.DGNi1

e s t e lNPUT 00TPUT' R =5.1 K .n.,10x , Av VOLTAGE * + 1" -1 S

g"" l l SOURCE - 2 1 3 3 4 SCD200 4 , 5 5 28VDC

6 T

8 ) c , D7

                                                           * = FLOATING OUTPUT
                                                                                            \

1 OPEN CIRCUlT FAULT TEST CONNECTION DIAGRAM I FIGURE 4-2A 051:I43.2]FlO42A.DONt1

e 2

                                                       -P0lNT OF SHORT CIRCUIT INPUT        OUTPUT' R =5.1 K .rt.101, l/sW b

VOLTAGE + + 1_ 1 y -wv I SOURCE - 2 2 X 3_ _3 4 SCD200 4 5 5

                                                                   ' 28VOC

6 7

e >

                                                         /
                                                     * = FLOATING OUTPUT l

SHORT CIRCUIT FAULT TEST CONNECTION DIAGRAM - FIGURE 4-2B OS1:(43,2] FIG 428.DGN!1

     ~
       . s l

r

                                                              -POINT OF SHORT CIRCUIT TO GROUND INPUT        QUTPUT'  o          RLa5. l K .n.101, %V VOLTAGE *

1., 1 y wv

[ SOURCE - 2 2 x 3_ 3 l 4 SCD200 4

                                                            ,              '28VDC +

5 5 , 6 i 7)E

J D7

                                                           + = FLOATING OUTPUT SHORT CIRCulT-TO-GROUND FAULT TEST CONNECTION DIAGRAM FIGURE 4-2C OSI:(43.2] FIG 42C.0GN:1

r g . J ., } PEN RECORDER S 1NPUT OUTPUT' e s x 1_ 10A,250VDC VOLTAGE *

_1 ^

0.5n q1%,22V V 140VAC SOURCE - 2 CHI CHI 2 SOURCE p , C : FCD400 : ( 5.1 K n.10% , %W

                                      ,   5     CH2          CH2     5 6_                         6
                                    '> 7-                            7

( 5.1 K A.10% , %W

                                      ) 8       CH3          CH3     8 9_                       _9 VOLTAGE *  +

10- ~10 SOURCE -

                                    \     11    CH4          CH4 11

( 5.1 K n .10% , %W

12. J2 13 13 .

g4 34

                                                                                            ,28VDC

15 16

c _ _ l D7

                                                                               * = FLOATING OUTPUT
                                  '                              ~

f, CH-1 CH-2 SCOPE

                                                      ~g EXT TRIG dc TRANSVERSE MODE FAULT TEST CONNECTION DI AGRAM FIGURE 4-2D OS1 (43.2] FIG 420.0GN;1

m

CL ~

l e t 1

     ,s ,                                                                                     u J

INPUT OUTPUT'

                     +
                                     '    ~
                                                           ~1                   V 480VAC VOLTAGE

1 SOURCE -

2 2 @ SOURCE

                           ,_ _      /                                       20A 600V 3_                _3 4     SCD200       4
                                                                          '28VDC

5 5 ,

6 8 ) u > D7 <

                                                                   * = FLOAT]NG OUTPUT CH-1 fl CH-2 i

i SCOPE EXT TRIG oc TRANSVERSE MODE FAULT TEST CONNECTION D1 AGRAM ~ FIGURE 4-2E OS1 (43.2IFIG42E DGN:1}}

ML20196E276: Difference between revisions

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ML20196E276: Difference between revisions

Latest revision as of 03:02, 13 November 2020

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